Phasor transducer apparatus and system for protection, control, and management of electricity distribution systems

ABSTRACT

A phasor monitoring system and apparatus for use with a distribution system for electricity wherein periodic three phase electricity is distributed in a plurality of circuits. The phasor monitoring apparatus comprises a phasor transducer that has an input that receives analog signals representative of parameters of electricity in a circuit of the distribution system, an analog to digital converter that receives the analog signals and outputs a digital data signal representative of the analog signals, a processor coupled to the analog to digital converter to receive the digital data signal output from the analog to digital converter, programming on the processor that computes phasor data representative of the electricity in the circuit based on the digital data received from the analog to digital converter and provides a digital output representative of the phasor data, and a network-compatible port coupled to the processor to transmit the phasor data onto a data network coupled thereto. The phasor monitoring system comprises a data network interconnecting a plurality of phasor transducers each associated with one of the circuits of an electricity distribution system. A phasor array processor is connected to the data network and receives phasor data from a plurality of the phasor transducers connected to the network. The phasor array processor computes combined phasor data for the plurality based upon the phasor data received from the plurality of phasor transducers.

RELATED APPLICATIONS

[0001] This application is a continuation under 37 C.F.R. §1.53(b) ofU.S. application Ser. No. 08/798,723, filed Feb. 12, 1997, pending,which is hereby incorporated by reference herein, and which was filed onthe same day as and incorporated by reference, U.S. patent applicationSer. No. 08/798,724, entitled “DIGITAL SENSOR APPARATUS AND SYSTEM FORPROTECTION, CONTROL, AND MANAGEMENT OF ELECTRICITY DISTRIBUTIONSYSTEMS”, filed on Feb. 12, 1997 herewith, the entire disclosure ofwhich is incorporated by reference herein.

BACKGROUND

[0002] The present invention relates to systems and components for theprotection, control, and/or energy management of electricitydistribution systems for electric utility, industrial, manufacturing,commercial, and/or institutional use.

[0003] Monitoring of electric parameters, such as current, voltage,energy, power, etc., particularly the measuring and calculating ofelectric parameters, provides valuable information for power utilitiesand their customers. Monitoring of electric power is important to ensurethat the electric power is effectively and efficiently generated,distributed and utilized. Knowledge about power parameters such asvolts, amps, watts, phase relationship between waveforms, KWH, KVAR,KVARH, KVA, KVAH, power factor, frequency, etc., is of foremost concernfor utilities and industrial power users. In addition, monitoring ofelectricity can be used for control and protection purposes.

[0004] Typically, electricity from a utility is fed from a primarysubstation over a distribution cable to several local substations. Atthe substations, the supply is transformed by distribution transformersfrom a relatively high voltage on the distributor cable to a lowervoltage at which it is supplied to the end consumer. From thesubstations, the power is provided to industrial users over adistributed power network that supplies power to various loads. Suchloads may include, for example, various power machines.

[0005] In such arrangements, utilities need to measure power coming outof or into the generating station or going into a power station. It isimportant to minimize the phase relationship between the current andvoltage waveforms of the power being transmitted to minimize losses. Itis also important to minimize the amount of harmonics that are presentin the voltage and current waveforms. Also, the ability to detect thepresence and magnitude of faults in the power system is important. Thus,accurate measurement of these waveforms is important.

[0006] In industrial applications, it is important to continuouslymonitor the voltage, current, phase, harmonics, faults and three phasebalance of the power into the machine. These parameters may vary withthe machine load. With knowledge of these parameters, the industrialuser can better adjust and manage the loads to control machines,determine alarm conditions and/or more efficiently use the power.

[0007] Many protection, control, and metering functions in a modem powerdistribution system require concurrent knowledge of the states ofmultiple circuits in the system in order to work efficiently andeffectively. Examples include differential protection devices andbreaker coordination schemes. Conventional devices and systems haveaddressed these requirements by various coordination and data sharingarrangements. Many of these approaches suffer from cost, performance,reliability, security, and scalability problems.

[0008] Accordingly, it is an objective of the present invention toprovide a system that overcomes the disadvantages of the prior art byproviding a monitoring system that can be used for protection, control,and/or metering of electricity in a electric distribution system.

SUMMARY

[0009] To achieve the foregoing and other objectives, there is providedan improved phasor monitoring system and apparatus for use with adistribution system for electricity wherein periodic three phaseelectricity is distributed in a plurality of circuits. The phasormonitoring apparatus comprises a phasor transducer that has an inputthat receives analog signals representative of parameters of electricityin a circuit of the distribution system. The phasor transducer alsoincludes an analog to digital converter that receives the analog signalsand that outputs a digital data signal representative of the analogsignals and a processor coupled to the analog to digital converter toreceive the digital data signal output therefrom. Programming on theprocessor of the phasor transducer computes phasor data representativeof the electricity in the circuit based on the digital data receivedfrom the analog to digital converter and provides a digital outputrepresentative of the phasor data. The phasor transducer also includes anetwork-compatible port coupled to the processor to transmit the phasordata onto a digital data network.

[0010] According to a further aspect, there is provided a phasormonitoring system for use with an electricity distribution system havinga plurality of circuits. The phasor monitoring system comprises a datanetwork interconnecting a plurality of phasor transducers. Each phasortransducer is associated with one of the circuits of the electricitydistribution system. One or more phasor array processors are connectedto the data network to receive phasor data from the plurality of phasortransducers connected to the network. The phasor array processorcomputes combined phasor data for the plurality of circuits in theelectricity distribution system based upon the phasor data received fromthe plurality of phasor transducers.

[0011] According to a further aspect, associated with each of thecircuits of the electricity distribution system is a protection device.The protection device is coupled to the data network. Each of theprotection devices is also connected to a circuit breaker associatedwith one of the circuits. The protection device operates its respectivecircuit breaker based upon data instructions received over the datanetwork.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a diagram illustrating a distribution system forelectricity incorporating embodiments of the present invention.

[0013]FIG. 2 is a schematic diagram of a phasor transducer device inFIG. 1.

[0014]FIG. 3 is a block diagram illustrating the functional programmodules of the phasor transducer device shown in FIG. 2.

[0015]FIG. 4 is a block diagram illustrating the functional programmodules of one of the phasor array processors shown in FIG. 1.

[0016]FIG. 5 is a diagram of a plurality of electric circuits used toillustrate an exemplary embodiment of the present invention.

[0017]FIG. 6 is a flow chart illustrating a first exemplary method foruse with the embodiments depicted in FIGS. 1-4.

[0018]FIG. 7 is a flow chart illustrating a second exemplary method foruse with the embodiments depicted in FIGS. 1-4.

[0019]FIG. 8 schematically represents a preferred embodiment of a systemusing a power monitoring unit of the present invention.

[0020]FIG. 9 schematically illustrates a preferred embodiment of aphysical layout of a preferred embodiment of a system of the presentinvention.

[0021]FIG. 10 schematically illustrates a preferred embodiment of theinternal structure of a power monitoring unit of the present invention.

[0022]FIG. 11 schematically illustrates a preferred embodiment of thedata acquisition module and its respective registers.

[0023]FIG. 11A shows a flowchart of a preferred embodiment of the logicfor the client portion of the data acquisition module.

[0024]FIG. 12 schematically illustrates a preferred embodiment of thepower meter module and its respective registers.

[0025] FIGS. 12A-12L show flowcharts of a preferred embodiment of thelogic for the client portion of the power meter module.

[0026]FIG. 13 schematically illustrates a preferred embodiment of theanalog input module and its respective registers.

[0027]FIG. 13A shows a flowchart of a preferred embodiment of the logicfor the client portion of the analog input module.

[0028]FIG. 14 schematically illustrates a preferred embodiment of theanalog output module and its respective registers.

[0029]FIG. 14A shows a flowchart of a preferred embodiment of the logicfor the client portion of the analog output module.

[0030]FIG. 15 schematically illustrates a preferred embodiment of thedigital input module and its respective registers.

[0031] FIGS. 15A-15B show a flowchart of a preferred embodiment of thelogic for the client portion of the digital input module.

[0032]FIG. 16 schematically illustrates a preferred embodiment of thedigital output module and its respective registers.

[0033] FIGS. 16A-16H show a flowchart of a preferred embodiment of thelogic for the client portion of the digital output module.

[0034]FIG. 17 schematically illustrates the inheritance of the registersand modules.

[0035]FIG. 17A schematically illustrates the inheritance of some of theregisters.

[0036]FIG. 17B schematically illustrates the inheritance of some of themodules.

[0037]FIG. 17C illustrates a hierarchical structure.

[0038]FIG. 18 schematically illustrates a preferred embodiment of theproperties of the modules.

[0039]FIG. 19 schematically illustrates a preferred embodiment of thedata flow for a module.

[0040] FIGS. 19A-19C show a flowchart of a preferred embodiment of thelogic for the module operation.

[0041]FIG. 20 schematically illustrates a preferred embodiment of theAND/OR module and its respective registers.

[0042] FIGS. 20A-20B show a flowchart of a preferred embodiment of thelogic for the client portion of the AND/OR module.

[0043]FIG. 21 schematically illustrates a preferred embodiment of theSetpoint module and its respective registers.

[0044] FIGS. 21A-21C show a flowchart of a preferred embodiment of thelogic for the client portion of the setpoint module.

[0045]FIG. 22 schematically illustrates a preferred embodiment of theEventLog module and its respective registers.

[0046]FIG. 22A shows a flowchart of a preferred embodiment of the logicfor the client portion of the EventLog module.

[0047]FIG. 23 shows an example application using the object orientedstructure of this invention.

[0048] FIGS. 24A-24B show the operation of the Module Flow Controller.

[0049]FIG. 25 schematically illustrates a preferred embodiment of theanalog output manager.

[0050] FIGS. 25A-25B show a flowchart of a preferred embodiment of thelogic for the application of a manager.

[0051]FIG. 26 schematically illustrates a preferred embodiment of thefeature manager.

[0052] FIGS. 26A-26B show a flowchart of a preferred embodiment of thelogic for the server portion of the feature manager.

[0053] FIGS. 27A-27C show a flowchart of a preferred embodiment of thelogic for the operation of a boolean register.

[0054] FIGS. 28A-28B show a flowchart of a preferred embodiment of thelogic for the operation of an enumerated register.

[0055] FIGS. 29A-29B show a flowchart of a preferred embodiment of thelogic for the operation of a numeric register.

[0056] FIGS. 30A-30B show a flowchart of a preferred embodiment of thelogic for the operation of a numeric bounded register.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0057] 1. General

[0058] Referring to FIG. 1, there is illustrated a diagram of anelectricity distribution system 10. The electricity distribution system10 represents a typical distribution system that may be used infactories or utilities, or in industrial, commercial, manufacturingand/or institutional uses. For example, the system 10 may represent apart of a typical three-phase electric switchgear or an electricitydistribution substation arrangement. Such an arrangement may be locatedin a manufacturing facility in which electrical energy is distributed toa plurality of loads, which may be various types of machines, motors,welding equipment, furnaces, mills, etc.

[0059] The distribution system 10 receives electric power over a powerline 20 from an electric utility 21. In the electricity distributionsystem 10, three phase electric power is distributed over a plurality ofthree-phase electric circuits, such as electric circuits 14, 15, 16, 17,and 18. Although only five three-phase circuits are illustrated in FIG.1, it is understood that the distribution system 10 may typicallyinclude many more such circuits.

[0060] As further illustrated in FIG. 1, one of the circuits, i.e. thecircuit 14, is a main circuit. The main circuit 14 feeds electricity toa three-phase substation bus 19. Multiple feeder or branch circuits,such as the three-phase circuits 15, 16, 17, and 18, obtain thethree-phase electric power from the substation bus 19. The feedercircuits 14, 15, 16, 17, and 18 distribute the electric power to aplurality of loads 25, 26, 27, and 28. (Note that instead ofdistributing electricity directly to a load, any of the feeder circuits,such as feeder circuits 15, 16, 17, and 18, may feed electricity toadditional distribution feeder circuits which in turn may distributeelectricity either directly to loads or to still additional feedercircuits. Also, note that the “load” for the main circuit 14 may beregarded as the combined loads of the feeder circuits 15-18.) Theelectricity distribution system 10 may also include numerous othercomponents found in typical installations, such as switches andtransformers.

[0061] Voltage sensors and current sensors are associated with each ofthe circuits. In one embodiment, a voltage sensor and a current sensorare associated with each of the phase conductors of each the circuits.For example, voltage sensors 29 and current sensors 30 are associatedwith the three phase conductors of the main circuit 14; voltage sensors31 and current sensors 32 are associated with the three phase conductorsof the feeder circuit 15, and so on. Also associated with each of theelectric circuits 14, 15, 16, 17, and 18, is a circuit breaker, such ascircuit breakers 44, 45, 46, 47, and 48. Although each of the circuitsin the system 10 of FIG. 1 has voltage and current sensors associatedwith it, in alternative embodiments, the electric distribution system 10may include additional electric circuits that do have voltage andcurrent sensors associated with them. In one embodiment, the voltage andcurrent sensors 29 and 30 associated with each circuit sense the powerwaveform for that circuit and provide an analog output representativethereof. In addition, although the embodiment of FIG. 1 shows voltagesensors and current sensors associated with each of the circuits in theinstallation, in alternative embodiment, some or all of the circuits mayhave only current sensors and no voltage sensors and similarly, some orall of the circuits may have voltage sensors and no current sensors.

[0062] 2. Phasor Transducer

[0063] Referring still to FIG. 1, associated with each of the circuitsis a phasor transducer. For example, associated with the main circuit 14is a phasor transducer 50, associated with the feeder circuit 15 is aphasor transducer 51, and so on. Each phasor transducer is connected toreceive the outputs from the voltage and current sensors associated withits respective circuit. For example, the phasor transducer 50, which isassociated with the main circuit 14, is connected to and receives theoutputs from the voltage sensors 29 and the current sensors 30; thephasor transducer 51, which is associated with the branch circuit 15, isconnected to and receives the outputs from the voltage sensors 31 andthe current sensors 32; and so on. Each of the phasor transducers isconnected to a digital data transmission network 60, as described inmore detail below.

[0064] Referring to FIG. 2, the branch circuit 15 is shown to comprisethree phase conductors, 15A, 15B, and 15C. The voltage sensors 31 areshown to comprise individual voltage sensors 31A, 31B, and 31C, eachassociated with its own respective phase conductor. The current sensors32 are shown to comprise the three current sensors, 32A, 32B, and 32C,each associated with its own respective phase conductor, 15A, 15B, and15C. The current sensors 32 also include the current sensor 32D which isassociated with the ground or neutral conductor in the circuit 15 andwhich measures the ground or neutral current in the circuit 15. In oneembodiment, the voltage and current sensors may be implemented usingconventional technology. For example, the voltage sensors may beconventional voltage transformers (e.g. PT's) and the current sensorsmay be conventional current transformers (e.g. CT's). (In low voltagesystems the PT's may be omitted.)

[0065]FIG. 2 shows a block diagram of the phasor transducer 51. Theother phasor transducers, 50, 52, 53, and 54, as well as any otherphasor transducers that may be associated with other circuits in thesystem 10, may be similar or identical in construction to the phasortransducer 51. The phasor transducer 51 has a plurality of inputs59A-59G to which the outputs of the voltage sensors 31 and currentsensors 32 are coupled. The phasor transducer 51 includes a conditionerunit 62. The conditioner unit 62 receives the voltage and current sensorsignals from the inputs 59A-59G. The conditioner unit 62 comprises twoparts: a voltage conditioner stage 62A and a current conditioner stage62B. Each of the voltage signals, V1, V2, and V3, received from thevoltage sensors 31A, 31B, and 31 C via the inputs 59A, 59B, and 59C areseparately conditioned in the voltage conditioner stage 62A to providelow level analog signals. Each of the current signals, I1, I2, I3, andI4, received from the current sensors 32A, 32B, 32C, and 32D via theinputs 59D, 59E, 59F and 59G are separately conditioned in the currentconditioner stage 62B to provide low level analog signals.

[0066] The low level analog signals from the conditioner unit 62 aresent to a multiplexer 64. The multiplexer 64 includes two parts orstages: a first stage 64A of the multiplexer 64 receives the low levelanalog signals representing the voltage signals from the voltageconditioning stage 62A and a second stage 64B of the multiplexer 64receives the low level analog signals representing the current signalsfrom the current condition stage 62B.

[0067] Each stage of the multiplexer 64 operates to select in turn whichof the conditioned analog signals from the conditioner unit 62 is to beoutput from the multiplexer 64 to an analog to digital converter 70. Theanalog to digital converter 70 includes two portions: a first analog todigital converter portion 70A and a second analog to digital converterportion 70B. The first analog to digital converter portion 70A receivesthe output of the first stage 64A of the multiplexer 64, including theselected one of the voltage signals. The second analog to digitalconverter portion 70B receives the output of the second stage 64B of themultiplexer 64 including the selected one of the current signals, I1,I2, I3, and I4. The analog to digital converter 70 repeatedly samplesthe analog signals and converts the samples to digital value outputs 76and 78 which represent the magnitudes of the analog voltage and currentsignals at the instant that they were sampled. The digital value outputs76 and 78 generated by the analog to digital converter 70 are output tobuffers 82. The digital value outputs 76 and 78 are retrieved from thebuffers 82 by a digital signal processor 90 which computes phasor data92 and 94 from the digitally-sampled data, as explained further below.The digital signal processor 90 outputs the phasor data 92 and 94 to aphasor transducer local microprocessor 100.

[0068] The phasor transducer local microprocessor 100 is coupled to oneor more communication ports 110 that connect the phasor transducer 51 tothe network 60. The communication port 110 may be a conventionalnetwork-compatible port such as a 10 base T ethernet port. The phasortransducer 51 may, optionally, include a local display 112 coupled tothe local microprocessor 100. The local display 112 may be used toprovide a local visual display of data, including volts, amps, watts,vars, power factor, frequency, etc., as well as provide energyconsumption recording of kwh, kvarh, kvah import, export and totals foreach circuit, or any combination of circuits. The phasor transducer 51may also include auxiliary local I/O ports 114 also coupled to the localmicroprocessor 100.

[0069] The phasor transducer 51 also includes a local synchronizationcircuit 120. In a preferred embodiment, the local synchronizationcircuit 120 utilizes two processes to provide a highly accurate localsynchronization timing clock signal 121 internal to the phasortransducer. First, the local synchronization circuit 120 receives anetwork synchronization signal 122 on an input port, such as data port110, which is connected to the network 60. This network synchronizationsignal 122 (which may be in a conventional UNIX time format) isgenerated by a network timing reference 123 coupled to the data network60. The network synchronization signal 122 synchronizes thesynchronization circuit 120 to within approximately 10 to 200milliseconds.

[0070] Referring to FIGS. 1 and 2, in a preferred embodiment, thesynchronization circuit 120 also receives a GPS-signal 126. TheGPS-signal 126 is obtained from a GPS receiver system 127. TheGPS-signal 126 is provided to each of the phasor transducers 51-54 usedin the electricity distribution system 10. The GPS receiver system 127may be a conventional type of GPS receiver that obtains GPS informationand provides the GPS signal 126 as an output. In one embodiment, asingle GPS receiver may be used for the entire installation containingthe electricity distribution system 10. Alternatively, more than oneGPS-receiver 127 may be used in the installation containing theelectricity distribution system 10 and some of the phasor transducersmay be coupled to receive a GPS signal from one of the GPS receivers andothers of the phasor transducer may receive a GPS signal from another ofthe GPS receivers. A single GPS receiver may be appropriate if theinstallation containing the electricity distribution system 10 does notcover too large a geographic area since propagation delays from the GPSreceiver to the phasor transducers should be taken into account. The GPSoutput signal 126 may be distributed to each of the phasor transducersby a suitable communication means, such a twisted pair, coaxial cable,wireless, and so on. In a still further embodiment, each of the phasortransducers 51-54 may have its own GPS receiver located internallythereto.

[0071] The GPS-signal 126 is used to fine tune the local synchronizationcircuit timing clock signal 121 to within approximately 1 microsecond.Using both the network synchronization signal 122 and the GPS signal126, the local synchronization circuit 120 outputs the localsynchronization timing clock signal 121 to the local microprocessor 100and to the analog-to-digital converters 70A and 70B.

[0072] The local microprocessor 100 receives the phasor data 92 and 94from the digital signal processor 90 and applies a time stamp to thedata using the local synchronization signal 121 from the synchronizationcircuit 120. The local microprocessor 100 outputs the phasor data asdigital data and transmits the phasor data output in real time via theports 110 onto the network 60. Optionally, the local microprocessor 100may process some or all of the phasor data prior to transmitting them inreal time over the network 60, as explained below.

[0073] 3. The Data Network

[0074] As mentioned above in connection with FIG. 1, the phasortransducers 50, 51, 52, 53 and 54 are connected to the data transmissionnetwork 60. The data transmission network 60 provides real time datacommunication among the various components connected to the network. Thedata transmission network 60 may be implemented using conventional localarea network (LAN) or wide area network (WAN) technology. The network 60may use conventional communications protocols, such as point-to-point ormulti-point data transmission. The network 60 should be able to sustainthe data flow generated by the various devices. Data propagation timesshould be short, deterministic and reliable.

[0075] Also connected to the data transmission network 60 are at leastone and preferably several phasor array processors, such as a firstphasor array processor 130, a second phasor array processor 131, a thirdphasor array processor 132 and so on. These phasor array processors 130,131, and 132 are connected as nodes on the network 60. It is understoodthat although only three phasor array processors are illustrated in FIG.1, there may be many more phasor array processors connected to thenetwork 60 in a typical embodiment. The structure and function of thephasor array processors are explained below.

[0076] The data transmission network 60 enables real time datacommunication between each of the phasor transducers 50, 51, 52, 53, and54 and the phasor array processors 130, 131, and 132. In addition, in apreferred embodiment, the data transmission network 60 enables datacommunication between the phasor array processors 130, 131, and 132, andfurther, the data transmission network 60 enables communication amongthe phasor transducers, if desired, and between the phasor transducersand the second and third phasor array processors 131 and 132. Stillfurther, the first phasor array processor 130 may be connected to localcomputers or remote computers, such as 136, 137, and 138, that are alsoconnected to the network 60, either locally or remotely. There may alsobe connected to the network other equipment such as programmable logiccontrollers and digital control systems.

[0077] In one embodiment, a TCP/IP ethernet communications network isused. TCP/IP ethernet is used due to its high data throughputcapabilities and its ability to be easily segmented to control dataloading and propagation times. For example, if each phasor transducercomputes and transmits voltages and current phasor arrays for all threephases of every cycle, and each phasor array has typically six elementsfor the odd harmonics, 1 to 11, the data throughput required per phasortraducer is approximately 300 kbaud including overheads. If a typicalsubstation has sixteen circuits, then the total data throughput would beabout 4800 kbaud. This is within the capabilities of LAN or WANtechnology, such as 10 base T ethernet, asynchronous transfer mode(ATM), or FDDI.

[0078] In alternative embodiments, the network may include digital radioor fiber optic data transmission techniques to couple the data. Thesealternatives also provide the advantage of providing electricalisolation between the various transducers, phasor array processor, andother nodes.

[0079] 4. The Phasor Array Processor

[0080] The phasor array processors, 130, 131, and 132, aremicroprocessor or computer-based devices that function as nodes toreceive data over the network 60 from the phasor transducers or fromother phasor array processors. For example, any one or more of thephasor array processors may include the appropriate hardware andsoftware to receive and process data from the phasor transducers, suchas the data output from the phasor transducer 51 on its output ports 110in FIG. 2.

[0081] Each of the phasor array processors may be implemented using ageneral purpose computer platform, such as an IBM-compatible personalcomputer. Alternatively, the phasor array processors may be implementedusing a custom-designed computing device. A custom-designed computingdevice may be used for higher performance for specific tasks.Custom-designed devices may include multiple processors or digitalsignal processors for very fast computational capabilities. Atask-specific hardware platform, such as a 7700 ION, manufactured byPower Measurement Ltd., of Victoria, BC, may be used.

[0082] The phasor array processor is preferably equipped with suitablehardware, such as RS-232, RS-485, ethernet or other industry standardcommunications ports, so that it is network-compatible with the network60. The phasor array processor 130 may also be equipped with multiplecommunication ports which would allow it to connect to multiple phasortransducer devices or multiple central computers, or to allow multiplephasor array processors to be connected to a remote computer.

[0083] 5. Protection Devices on the Data Network

[0084] Also connected to the data transmission network 60 are one ormore protection devices (also referred to as protection device nodes).In one embodiment, a protection device is associated with each of thecircuits. For example, a first protection device 184 is associated withthe first circuit 14, a second protection device node 185 is associatedwith the second circuit 15, and so on. Alternatively, there may be moreor fewer protection devices than circuits. The protection devices aremicroprocessor or computer-based devices or nodes that can receive dataover the network 60 from the phasor transducers 50-54 or the phasorarray processors 130-132, as well as from other devices on the network60. In a preferred embodiment, the protection devices process data usingobject-oriented program modules, as explained in more detail below.

[0085] The protection devices may be implemented using a general purposecomputer platform. For example, the protection device node mayimplemented on an IBM-compatible personal computer or on a task-specifichardware platform. Each protection device is preferably equipped withsuitable hardware, such as RS-232, RS-485, ethernet or other industrystandard communications ports, so that it is network-compatible with thenetwork 60. Each of the protection devices has one or more outputs thatare connected to the circuit breakers associated with the circuits. Inthe embodiment wherein there is one protection device for each circuit,each of the protection devices may have a single output coupled to itsrespective circuit breaker for its respective circuit. For example, theoutput of the first protection device 184 is connected to the circuitbreaker 44 associated with the main circuit 14, the output of theprotection device 185 is connected to the circuit breaker 45 associatedwith the branch circuit 15, and so on. In the alternative embodimentwhere there are fewer protection devices than circuits, at least one ofthe protection devices has more than one output and is coupled to morethan one of the circuit breakers.

[0086] The protection devices may be coupled directly to the circuitbreakers, or alternatively, each of the protection devices may have adata output that is coupled to the data network 60. In this latterembodiment, the circuit breakers 44-48 each have a port coupled to thenetwork 60 to receive data addressed thereto from the one or moreprotection devices.

[0087] In one embodiment, a first protection device operates to provideoutputs to some or all of the circuit breakers in the distributionsystem. Another protection device operates to back up the firstprotection device. According to this embodiment, the second protectiondevice is configured similar to the first protection device so that itsoperation follows that of the first protection device. The secondprotection device takes over for the operation of the first protectiondevice if the first protection device fails.

[0088] 6. Operations and Program Objects

[0089] The phasor array processors have four principle functions:protection, control, energy management, and systems diagnostics. Anindividual phasor array processor can provide any combination of thesefunctions depending on the hardware, software, and/or software/firmwareand the requirements of the user.

[0090] According to a present embodiment, the phasor transducers andphasor array processor(s) include appropriate software, such asprogramming and logic, to implement the desired functions, features, andoperations. The software may be implemented in alternative waysincluding various programming languages, scripts, and architectures, andcombinations of software and firmware, etc. In one preferred embodiment,the phasor transducers, phasor array processors, and other components onthe network 60 interact internally and with each other using anobject-oriented programming architecture. One preferred object-orientedprogramming approach is disclosed in the copending patent applicationSer. No. 08/369,849, now U.S. Pat. No. 5,650,936, the entire disclosureof which, including the microfiche appendix, is incorporated byreference herein and the text of which is replicated below.

[0091] If a phasor array processor is implemented using anIBM-compatible personal computer, the personal computer may run theVirtual ION Processor software developed by Power Measurement Ltd. ofVictoria, BC. This software allows standard ION modules to beimplemented on an IBM-compatible personal computer. The IONcommunication architecture allows the inputs or outputs of any IONmodule on the phasor array processor to be linked to the inputs oroutputs of any ION module on the phasor transducers via standardcommunications networks.

[0092] ION Architectural Description (Incorporated from U.S. Pat. No.5,650,936)

[0093] An object oriented architecture is used within individualmonitoring units. The monitoring devices include circuitry whichreceives an electrical signal and generates at least one digital signalrepresenting the electrical signal. Objects within such individualmonitoring units include modules which perform a function and registerswhich contain the inputs, outputs and setup information for the modules.Methods can be invoked on all objects to change or query the operationor configuration of the device. At least one of the modules receives thedigital signal as an input and uses the signal to generate measuredparameters. Additional modules take measured parameters as input andgenerate additional parameters therefrom. The module may be linked in anarbitrary manner to form arbitrary functional blocks.

[0094] The present embodiments relate generally to digital powermonitoring. More specifically, the embodiments relate to a digital powermonitoring system using an object oriented structure. The presentembodiments also generally relate to an improved object orientedstructure.

[0095] Monitoring of electrical power, particularly the measuring andcalculating of electrical parameters, provides valuable information forpower utilities and their customers. Monitoring of electrical power isimportant to ensure that the electrical power is effectively andefficiently generated, distributed and utilized. As described in moredetail below, knowledge about power parameters such as volts, amps,watts, phase relationship between waveforms, KWH, KVAR, KVARH, KVA,KVAH, power factor, frequency, etc. is of foremost concern for utilitiesand industrial power users.

[0096] Typically, electricity from a utility is fed from a primarysubstation over a distribution cable to several local substations. Atthe substations, the supply is transformed by distribution transformersfrom a relatively high voltage on the distributor cable to the lowervoltage at which it is supplied to the end consumer. From thesubstations, the power is provided to industrial users over adistributed power network which supplies power to various loads. Suchloads may be, for example, various power machines.

[0097] In such arrangements, utilities need to measure power coming outof the generating station or going into a power station. It is alsoimportant to minimize the phase relationship between the current andvoltage waveforms of the power being transmitted to minimize losses.Thus, accurate measurement of these waveforms is important.

[0098] In industrial applications, it is important to continuouslymonitor the voltage, current and phase of the power into the machine.These parameters may vary with the machine load. With knowledge of theseparameters the industrial user can better adjust, and control the loadsto control machines, determine alarm conditions and/or to moreefficiently use the power.

[0099] Various different arrangements are presently available formonitoring, measuring, and controlling power parameters. Typically, anindividual power measuring device which measures specific power systemparameters is placed on a given branch or line proximate one of theloads. Such power monitoring devices measure electrical powerparameters, such as those described above.

[0100] An example of such a system is disclosed in U.S. Pat. No.5,151,866. In the system disclosed in this patent, a power analyzersystem uses discrete analog transducers to convert AC voltage andcurrent signals from a power system to DC output signals. The valuesfrom the voltage and the current transducers are then used to calculatethe various other desired power parameters.

[0101] In addition to monitoring power parameters of a certain load,power monitoring devices have a variety of other applications. Forexample, power monitoring devices can be used in supervisory control anddata acquisition systems (SCADA), process controllers (PLC), etc.

[0102] As discussed briefly above, in industrial applications, aplurality of the power monitoring units are placed on the branches of apower distribution system near the loads. The monitoring units areconnected through a communication network to at least one centralcomputer. An example of such system is disclosed in Siemens PowerEngineering & Automation VII (1085) No. 3, Pg. 169, Microprocessor—BasedStation Control System For New And Existing Switchgear, Muller et al.

[0103] In fact, many other applications also use a network of devicesinterconnected through some sort of communication media. Often, thenetwork is composed of a large number of slave devices with a muchsmaller number of master devices. A master device is any device that canquery another device or change the configuration of another device. Aslave device is a device that performs a function, and produces resultsthat can be accessed by another device. It is possible for a singledevice to act as a master and a slave. In the power monitoring systemdescribed above, the central computer is the master device and theindividual power monitoring units are the slave devices.

[0104] The architecture of the slave devices is such that they contain alarge number of registers. Some of these registers contain output valuesfrom the slave device which can be read by the master and some of theseregisters contain setup information for the slave device which themaster can read or write. The master device must know which registerscontain which information for every different slave device. For instancethe master device would know that a certain device measures volts and itwould know that volts are stored in a particular register. Therefore, inorder for the master to retrieve a reading of volts from the slavedevice it must send a request (communications packet) to the slavedevice indicating that it requires a packet containing the number in therespective register.

[0105] With this approach, the master device(s) must have a large amountof knowledge about the configuration of the remote devices. Thisrequires large amounts of storage space on the master device(s). Also,if the characteristics of a slave device are changed, or a new type ofslave device is added, the master device(s) must be reprogrammed. If theslave devices go through a large number of changes, the master device(s)must retain information about the slave devices for all intermediateversions to retain backward compatibility. This further increases thememory and processing power requirement for the master device(s).

[0106] In the configuration where the slave device is fieldprogrammable, the master device(s) must have some means of determiningthe slave device's current configuration. In addition the masterdevice(s) must be able to change the slave device's configuration. Thisinvariably means that the master device(s) must know all the possibleconfigurations of the remote device which again increases the memory andprocessing power required for the master device.

[0107] Further, if there are multiple masters changing the configurationof the same slave device, it is difficult for the masters to keep trackof the current configuration of the device. Each master has its ownlocal copy of the current configuration of the slave device. Whenanother master changes the configuration of the device, the firstmaster's local copy is not updated. Thus, the first master may think thedevice is executing a function it no longer is.

[0108] If the configuration of a slave device is not configurable or ifthe slave device has limited configurability, the slave device may beusing its available resources (memory and processing power) to performfunctions that the user has no interest in. Therefore, the slave devicemay perform many functions that are not required, but may be missingsome functions that are required by a certain user.

[0109] Systems are available which use an object oriented approach toprogram a computer to connect the outputs of a number of remote devicesto local functions on the computer and to the inputs of other devices.U.S. Pat. Nos. 4,901,221, 4,914,568 and 5,155,836 disclose such systemswhere a central digital computer is connected to a number of remotedevices. In the systems disclosed in these patents, however, the objectoriented structure resides on the central digital computer and allinformation must travel through the central computer. Therefore, thespeed of the system is limited to the speed of the communicationschannels between the computer and the remote devices and the speed ofthe computer. Further, although the structure on the computer can bemodified through the object oriented architecture the slave devicescannot be easily modified or updated.

[0110] Systems are also available which allow reprogramming of a slavedevice. For example, such a system is disclosed in U.S. Pat. No.5,155,836. The controlling logic within these devices, however, does notallow the reconfiguration of the device while other functions within thedevice continue to operate. The user must compile and download firmwarein order to implement a different control program. The downloadingprocess interrupts the operation of the device.

[0111] Therefore, in view of the above it is a primary object of thepresent embodiments to provide a power monitor which can be readilyconfigured to exactly match a user's unique requirements.

[0112] It is a further object of the present embodiments to provide apower monitoring system where it is not necessary to change the softwareon a master device when a slave device is upgraded.

[0113] It is a further object of the present embodiments to provide apower monitoring system where the storage space memory and/or processingpower required for master device(s) is minimized.

[0114] It is still a further object of the present embodiments toprovide a power monitoring system where master device(s) can accuratelyand easily track changes or modifications in the configuration ofindividual monitoring units devices.

[0115] To achieve these and other objectives, the present embodimentsuse an object oriented architecture within individual digital devices,such as monitoring devices. The monitoring devices include circuitrywhich receives an electrical signal and generates at least one digitalsignal representing the electrical signal. Objects within suchindividual monitoring units include modules which perform a function andpreferably registers which contain the inputs, outputs and setupinformation for the modules. Methods can be invoked on all objects tochange or query the operation or configuration of the device. At leastone of the modules receives the digital signal as an input and uses thesignal to generate measured parameters. Additional modules take measuredparameters as input and generate additional parameters therefrom.

[0116] In one preferred embodiment, the monitoring device includestransducers which measure voltage and current from a power line.

[0117] In another preferred embodiment, a flow controller is used tocontrol the operation of the modules. A feature manager provides a meansfor accessing the entire device.

[0118] Since, the objects reside inside the individual slave devices thecommunication between the different objects is limited only by theprocessing speed of the individual monitoring units and not by the speedof the communications media between the devices. With this arrangementthe number of slave devices connected to a single master is virtuallyunlimited since no communication between the devices is required unlessa specific request from the user is made.

[0119] The operations that the monitoring unit performs are configuredby a master device executing methods which instruct the monitoring unitto connect modules to registers. The objects can be programmed andlinked in totally arbitrary ways, enabling the user to build arbitraryfunctional blocks consisting of networks of objects.

[0120] Many modifications to the preferred embodiment will be apparentto those skilled in the art. It is the intention of this description toprovide an example system using the disclosed embodiments.

[0121] The present embodiments comprise a novel system with an objectoriented structure. The novel system and architecture are particularlyuseful for configuring a power monitoring unit to perform givenfunctions and causing the unit to execute those functions.

[0122]FIG. 8 schematically illustrates how a power monitoring unit 900using the present embodiments is connectable to a three wire power line.Three current transducers (CTs) 902A, 902B and 902C are connected towires 901A, 901B and 901C of the power line, respectively. Potentialtransducers (PTs) 904A and 904B are connected between lines 901A, 901Band 901B, 901C, respectively. A plurality of fuses 906 are disposedbetween the lines 901A-901C and Pts 904A and 904B. Fuses 910 areconnected between Pts 904A and 904B and unit 900.

[0123] The CTs 902A-902C are connected through a shorting switch or testblock 908 to the power monitoring unit 900. The CTs 902A-902C providethe power monitoring unit 900 with current inputs I11-I32. The PTs 904Aand 904B provide the power monitoring unit 900 with voltage inputsV1-V3. Current inputs I41 and I42, chassis ground 912 and voltage inputVREF are connected to ground potential. The unit 900 is connected to apower supply, such as a standard 120 V AC supply, through power leads Land N.

[0124]FIG. 9 shows a preferred embodiment of the physical layout of aplurality of monitoring units 900 in a system using the presentembodiments. The system comprises one or more personal computers (PCs)914 which are used as master devices. A plurality of monitoring units900 configured as intelligent electronic devices (IEDs) are used asslave devices. Virtual intelligent electronic devices (VIEDs) 915 whichreside in software on the personal computer 914 can also serve as slavedevices. All devices in the system are interconnected through acommunication network 916. The network may be directly connected todevices or may connect through other communications devices such asmodems 912. Preferably, the IEDs, PCs and VIEDs all have an objectoriented architecture as described in detail below.

[0125] To fully appreciate the present embodiments, an understanding ofthe principals of basic object oriented structures is necessary.Therefore, a brief description of the type of architecture is givenhere. (A more detailed discussion of the principles of object orientedstructures is given in “SMALLTALK-80 The Language And ItsImplementation,” Goldberg and Robson, 1983 (from which some of thefollowing definitions are taken)). An object consists of some privatememory and a set of operations. An object has state, behavior andidentity. The nature of the object's operations depends on the type ofcomponent it represents. For example, objects representing numberscompute arithmetic functions, and objects representing data structuresstore and retrieve information. A key component of object orientedarchitecture is encapsulation. Encapsulation is the process of hidingall of the details of an object, as well as the implementation of itsmethods. In an object oriented system, in order for an object to carryout one of its operations, a request must be made which specifies whichoperation is desired. The request is called a “message”. Importantly,because of encapsulation in object oriented architecture, the messagedoes not specify how that operation is to be carried out. The“receiver”, the object to which the message was sent, determines how tocarry out the requested operation. The set of messages to which anobject can respond is called its “interface” with the rest of thesystem. The only way to interact with an object is through itsinterface. A crucial property of an object is that its private memorycan be manipulated only by its own operations. Messages are the only wayto invoke an object's operations. These properties ensure that theimplementation of one object cannot depend on the internal details ofother objects, only on the messages to which they respond.

[0126] Messages ensure the modularity of the system because they specifythe type of operation desired, but not how the operation should beaccomplished.

[0127] Other important components of object oriented architecture are“classes” and “instances”. A class describes the implementation of a setof objects that all represent the same kind of component. The individualobjects described by a class are called its instances. A class describesthe form of its instances' private memories and it describes how theycarry out their operations. Even an object that represents a uniquecomponent is implemented as a single instance of a class. The instancesof a class are similar in both their public and private properties. Anobject's public properties are the messages that make up its interface.All instances of a class have the same message interface since theyrepresent the same kind of component. An object's private properties area set of instance variables that make up its private memory and a set ofmethods that describe how to carry out its operations. The instancevariables and methods are not directly available to other objects. Theinstances of a class all use the same set of methods to describe theiroperation.

[0128] Each method in a class tells how to perform the operationrequested by a particular type of message. When that type of message issent to any instance of the class, the method is executed. A classincludes a method for each type of operation its instances can perform.The method may specify some changes to the object's private memoryand/or some other messages to be sent. A method also specifies a valuethat should be returned. An object's methods can access the object's owninstance variables, but not those of any other objects.

[0129] Another important aspect of the objects within the device is thatthey are independent or autonomous. In other words, any change in theconfiguration of one object on a slave by a master device does notaffect the operation of the other objects on the slave device (or anyobjects on the master device).

[0130] Referring now to FIG. 10, a preferred embodiment of the internalstructure of an IED 900 is illustrated. As described in more detailbelow, the IED's 900 are run by an object oriented structure. Theelectrical signals (i.e. the voltage and current) from the power linesare used by a detector to generate digital signals which represent theelectrical signals. In the illustrated embodiment, the detector iscomprised of the CTs 902, PTs 904, conditioning circuitry and A/Dconverters, as described more fully below. Three-phase voltage andcurrent input signals V1-V3 and I1-I4 from electric power lines enterthe motherboard 825 and are converted to voltage levels compatible withthe analog to digital converters (A/Ds) 829 and 830 by signalconditioning circuitry 823. In an exemplary embodiment a suitable A/Dconvertor is a 13 bit, 7 input one available from National Semiconductoras model No. LM12458. A suitable voltage to the A/D's 829 and 830 rangesfrom 0 to 5 Volts depending on what part of the AC signal the sample istaken at and the level of the AC signal.

[0131] In the illustrated embodiment, the signal conditioning circuitrycomprises operational amplifiers (op amps) 860, 862 and 864 andassociated circuitry which amplify V1, V2 and V3 respectively. Thecurrents I1, I2, and I3 are amplified by two different scales to providegreater dynamic range. The amplification to the two different scales isimplemented using the conditioning circuitry 823. Op amps 866A, 866B and866C amplify input current signals I1, I2 and I3, respectively, to afirst scale. For example, a current of 5 Amperes AC creates a voltage of4 Volts AC to the A/D converter. Op amps 868A, 868B and 868C amplifyinput current signals I1, I2 and I3, respectively to a second scale. Forexample, a current of 100 Amperes AC creates a voltage of 4 Volts AC tothe A/D converter. The voltage and current signals enter separate A/Ds829 and 830 so that the voltage and current on a particular phase can besimultaneously sampled. Auxiliary Input Signals 820 on the AUX board 824also pass through signal conditioning circuitry 822 and to A/D 829.Auxiliary inputs allow the user to sample additional signals in additionto the three-phase voltage and current. For example, the auxiliaryinputs may be 0 to 10 Volts DC outputs from a temperature transducer.

[0132] A digital signal processor (DSP) 828 reads the samples from theA/D converters 829, 830 through the A/D Bus 831. The signals arepreferably sampled at the rate of 128 samples per line frequency cycle.The DSP performs a Fast Fourier Transform (FFT) on the samples todetermine the frequency components of the signal in a manner known inthe art. It also calculates Root Mean Square (RMS) voltage and/orcurrent for each input signal. This data is then transferred throughdual port RAM 827 to the microcontroller 835. A suitable DSP is a 4Kbyte RAM available as a TMS320C25 available from Texas Instruments.

[0133] The microcontroller 835 performs many functions within the IED.The fundamental frequency to square wave converter 843 provides a squarewave at the fundamental frequency of the incoming voltage signals. Asuitable fundamental frequency to square wave converter is an LM311Davailable from National Semiconductor configured in a manner known inthe art. A time processing unit (TPU) within the microcontroller 835measures this frequency and multiplies it by a predetermined value, suchas 128. The TPU creates an A/D sample clock 842 at this new frequency sothat the A/Ds sample at 128 samples per cycle. A suitablemicrocontroller is a MC68332ACFC16 available from Motorola.

[0134] Different AUX boards 824 and motherboards 825 can be exchangedwith different CPU Boards 846. This, however presents a calibrationproblem. In the system of the present embodiments, the calibrationinformation for the circuitry 822, 823 of each AUX or motherboard ispreferably stored on the individual board. A suitable EEPROM in a 93LC56available from Microchip. This is implemented by storing the informationin calibration constants EEPROM 839, 840 on each individual board. Themicrocontroller 835 then reads the information using the synchronousserial communications bus 838 before performing calculations on thevalues received through the dual port RAM 827 from the DSP 828. Thesynchronous serial communications bus 838 is also used to communicatewith the display 851. Results of all calculations and control functionsof the microcontroller 835 can be displayed on the display.

[0135] The IED 900 connects to the network 916 through thecommunications board 848. The microcontroller 835 sends and receivesinformation over the serial communications bus 847.

[0136] A further description of a preferred embodiment of the presentembodiments and its operation is given in U.S. patent application Ser.No. 08/367,534 filed concurrently with this application and entitled“High Accuracy Power Monitor and Method” which is incorporated herein byreference.

[0137]FIGS. 11, 12, 13, 14, 15 and 16 show how the auxiliary inputsignals 820, the voltage and current input signals 821, and the digitalI/O signals 844 may be represented in the object oriented structure ofthis embodiments. In an exemplary embodiment, in the IED 900 the logicor code is implemented in firmware and in the PC the code is implementedin software. It will, of course, be recognized by those skilled in theart that the logic for the IED 900 can also be implemented in softwareand that the logic in the PC can be implemented in firmware. In thepresent embodiment, the firmware is implemented using a 512K byte flashEEPROM 834 available from Intel as a 28F010 EEPROM. In an exemplaryembodiment, the software is written in the C programming language. Anexemplary embodiment of the logic for the object oriented architectureof the present embodiments in object code is given in microficheAppendix A which is incorporated herein by reference. The object code ispresented in Srecord format which is defined in the M68332BUG DebugMonitor User's Manual (Motorola 1990) which is incorporated herein byreference. More detailed schematics for the presently preferredembodiment are given in microfiche Appendix B which is incorporatedherein by reference.

[0138] In the system of the present embodiments, two fundamental classesexist for objects: 1) registers and 2) modules. Both the registers andmodules are derived from a common base class (class=1). The registersare passive data storage objects containing a single value, an array orstructure. Registers behave only as “servers” in the architecture. A“server” is defined as an entity which can respond to methodinvocations. A “client”, on the other hand, is an entity which caninvoke a method on a server. Modules behave both as client and server.The client portion of the module contains the active components thatperform the various tasks within the device. The inheritance of theregisters and modules is shown in FIG. 17. An inheritance diagram forsome of the registers is shown in FIG. 17A. An inheritance diagram forsome of the modules is shown in FIG. 17B. Data passing between objectsis accomplished using method invocation using “types,” where typesdefine the semantics for passing data between objects. A method isinvoked by a “client” sending a message to another object. This messagecontains a “method” and may contain a “value”. Every method in an objecthas a security level. Any methods which are invoked with a level lessthan the security level for that method will fail. The system also hasthe following set of rules of operation which must be followed byobjects:

[0139] 1. All data passed to or from an object must have a Type.

[0140] 2. Modules must be owned by a module, with the exception of theroot module, which has no owner.

[0141] 3. Registers must be owned by a module.

[0142] 4. Behavior of servers will be consistent for multiple clients.

[0143] 5. A server portion of a object cannot access the server portionof another object.

[0144] 6. A client portion of an object cannot access the client portionof another object.

[0145] 7. Any register or module cannot be destroyed if it is owned byany module.

[0146] The system also has a hierarchy. As used herein a hierarchy meansthat every manager, module and register can be accessed by starting atthe top of the hierarchy. This concept can be seen pictorially byreferring to FIG. 17C. In this figure modules or registers that appearsas setup registers are connected to the bottom of the modules ormanagers with a line. Registers that appear as output registers areconnected with lines to the right side of the modules and registers thatappear as input registers are connected with lines to the left of themodules.

[0147] Certain semantics are needed for passing information to and frommodules and registers. Here these semantics are defined by “Types”.Table A provides the Types defined in the presently preferredembodiment. TABLE A The Types describe the semantics for passinginformation to and from modules and registers. Type Name Typeequivalence Restrictions Description VoidType fundamental Type Has nosemantic value. SignedType fundamental Type Maximum size = Defines asigned 32 bits. value. UnsignedType fundamental Type Maximum size =Defines an 32 bits unsigned value. CharType fundamental Type Maximumsize = Defines a 32 bits. character value. Supports wide characters aswell as ASCII. BooleanType fundamental Type Size = 1 bit. Defines aBoolean value. Value may be TRUE or FALSE. FixedPointType fundamentalType Maximum size = Defines a fixed 64 bits. point value. FloatTypefundamental Type Size = 32, 64, or Defines a floating 80 bits. pointvalue. ComplexType fundamental Type Maximum size = Defines a TBA.complex value. DeltaType fundamental Type Size = 0 bits. The valuerepresents a delta-function pulse. RealType define union RealType =Defines a real SignedType.linevert split. value. UnsignedType.linevertsplit. CharType.linevert split. BooleanType.linevert split.FloatType.linevert split. FixedPointType. NumericType define unionDefines a NumericType = numeric value. RealType.linevert split.ComplexType. SignedArrayType define array Defines an array ofSignedArrayType = signed values. {SignedType {grave over ( )}value.sub.i{grave over ( )}}. UnsignedArrayType define array Defines an array ofUnsignedArrayType = unsigned values. {UnsignedType {grave over( )}value.sub.i {grave over ( )}}. CharArrayType define arrayCharArrayType = Defines an array of {CharType {grave over ( )}char.sub.i{grave over ( )}}. characters. BooleanArrayType define array Defines anarray of BooleanArrayType = Boolean values. {BooleanType {grave over( )}value.sub.i {grave over ( )}}. FixedPointArrayType define arrayDefines an array of FixedPointArrayType = fixed point values.{FixedPointType {grave over ( )}value.sub.i {grave over ( )}}.FloatArrayType define array FloatArrayType = Defines an array of{FloatType {grave over ( )}value.sub.i {grave over ( )}}. floating pointvalues. ComplexArrayType define array Defines an array ofComplexArrayType = complex values. {ComplexType {grave over( )}value.sub.i {grave over ( )}}. NumericArrayType define union Definesan array of NumericArrayType = numeric values. SignedArrayType.linevertsplit. UnsignedArrayType.linevert split. CharArrayType.linevert split.BooleanArrayType.linevert split. FixedPointArrayType.linevert split.FloatPointArrayType.linevert split. ComplexArrayType. ArrayUnsignedArraydefine structure Structure defines an Type ArrayUnsignedArrayType =array of {UnsignedArrayType UnsignedArrayTypes. {grave over( )}us.sub.-- array.sub.i {grave over ( )}}. StringType defineStringType = must be null Defines a character CharArrayType. terminated.string (null-terminated). StringArrayType define structure Defines anarray of StringArrayType = strings. {CharArrayType {grave over( )}string.sub.i {grave over ( )}}. SizeType define SizeType = Anunsigned integral UnsignedType. value which is used for defining a sizeparameter (e.g. size of array, #records). CounterType define CounterType= An unsigned integral UnsignedType. value which can be incremented (by1 or more), decremented (by 1 or more), and cleared to 0. IndexTypedefine IndexType = An unsigned integral UnsignedType. value which isused to index arrays. TimeType define TimeType = Universal Time (GMT) inNumericType. seconds. ReasonType define ReasonType = The reason for anCharArrayType. exception. ExceptionType define structure ExceptionType =An exception returns a UnsignedType code and value. A {grave over( )}exception.sub.-- cause. reason string is Type opitonal. {grave over( )}exception.sub.-- value{grave over ( )} The valid codes are:[ReasonType {grave over ( )}reason{grave over ( )}]. 0 = underflow 1 =overflow 2 = not.sub.-- valid 3 = not.sub.-- supported 4 = not.sub.--available 5 = invalid.sub.-- method 6 = loss.sub.-- of.sub.-- precision.7 = internal.sub.-- error MethodType define The value representsMethodType = UnsignedType. (numerically) the particular method of anObject. ClassType define ClassType = The value represents UnsignedType.(numerically) a particular class (such as Numeric Register of PowerMeterModule). NodeHandleType define union NodeHandleType = An address to aremote StringType.linevert split. IED site. UnsignedType.ExtendedHandleType define structure Defines a handle usedExtendedHandleType = to a reference an object [NodeHandleType {graveover ( )}node{grave over ( )}] on another IED. UnsignedType {grave over( )}handle{grave over ( )}. HandleType define union HandleType = Thevalue represents UnsignedType.linevert split. the address of anExtendedHandleType. object. ExtendedHandle define structure array Thevalue is an array of ArrayType ExtendedHandleArrayType = ExtendedHandles. {ExtendedHandle {grave over ( )}value.sub.i {grave over ( )}}.HandleArrayType define union HandleArrayType = The value is an array ofExtendedHandleArrayType.linevert split. handle values.UnsignedArrayType. PriorityType define Priorities range from 0 The valuerepresents an PriorityType = UnsignedType. to 255 priority. Guidelinesfor priorities are as follows: Urgent 192 to 255 High 128 to 191 Medium64 to 127 Low 0 to 63 RangeType define structure RangeType = defines arange of IndexType values that starts at {grave over ( )}range.sub.--start{grave over ( )} index range.sub.-- start and IndexType ends atindex {grave over ( )}range.sub.-- end{grave over ( )}. range.sub.--end. This is useful in log situations. EventType define structureEventType = Defines a structure for PriorityType {grave over( )}priority{grave over ( )} an event. UnsignedType Values forevent.sub.--state {grave over ( )}event.sub.-- state{grave over ( )}are: HandleType 0 = unary state event. {grave over ( )}cause.sub.--handle{grave over ( )} 1 = Active transition IONType for bi-state event.{grave over ( )}cause.sub.-- value{grave over ( )} 2 = Inactivetransition HandleType for bi-state event. {grave over ( )}effect.sub.--handle{grave over ( )} 3 = Label change IONType event. {grave over( )}effect.sub.-- value{grave over ( )}. LogHeaderType define Structuredefines the LogHeaderType = header for a general HandleArrayType purposelog record. LogRecordType define structure LogRecordType = Structuredefines the IndexType {grave over ( )}position{grave over ( )} datavalues in a general TimeType purpose log record. {grave over( )}timestamp{grave over ( )} {Type {grave over ( )}value.sub.i {graveover ( )}}. LogArrayType define structure.sub.-- array Array of logrecords. LogArrayType = {LogRecordType {grave over ( )}logrec.sub.i{grave over ( )}}. WaveformType define structure Defines a structure forWaveformType = a waveform. NumericType Note: {grave over( )}sampling.sub.-- frequency{grave over ( )} plotted value =NumericType {grave over ( )}offset{grave over ( )} (data point +NumericType {grave over ( )}scale{grave over ( )} offset) * scale.TimeType {grave over ( )}time.sub.-- of.sub.-- first.sub.-- point{graveover ( )}. NumericArray {grave over ( )}points{grave over ( )}.AlarmType define structure AlarmType = Structure for alarms: HandleTypeWhen parameter {grave over ( )}effect.sub.-- handle{grave over ( )}Transitions is odd the CounterType alarm is active. {grave over( )}transitions{grave over ( )}. PriorityType {grave over( )}priority{grave over ( )}. AlarmArrayType define structure.sub.--array Array of alarms. AlarmArrayType = {AlarmType {grave over( )}alarm.sub.i {grave over ( )}}. SecurityType define Value representsa SecurityType = UnsignedTypes. security level. The following securitylevels are defined:  1 = no access 16 = user (R/O) 32 = user (R/W) 48 =configure (can create/destroy modules) 64 = system administration (canchange secruity levels). 80 = highest level (factory - i.e. calconstants) MehtodSecurityType define structure Assigns a security levelMethodSecurityType = to a method. MethodType {grave over( )}method{grave over ( )} SecurityType {grave over ( )}security{graveover ( )}. MethodSecurityArray define structure.sub.-- array Array ofmethod- Type MethodSecurityArrayType = security. {MethodSecurityType{grave over ( )}methsec.sub.i {grave over ( )}}. CompositeLogRecorddefine structure This is the complete CompositeLogRecord = descriptionof a log UnsignedType record. {grave over ( )}record.sub.-- type{graveover ( )} Note:-the position field HandleType {grave over( )}handle{grave over ( )} of the log record type is LogHeaderType{grave over ( )}header{grave over ( )} the record ID. [StringArrayType{grave over ( )}labels{grave over ( )}] RecordType is currentlyLogArrayType {grave over ( )}records{grave over ( )}. always zero.CompositeLogArray define structure.sub.-- array An array ofCompositeLogArray = CompositeLogRecords {CompositeLogRecord {grave over( )}record.sub.i {grave over ( )}}. CompositeEventRecord definestructure This is a complete CompositeEventRecord = description of asingle UnsignedType event (either unary {grave over ( )}record.sub.--type{grave over ( )} event or half of a HandleType {grave over( )}handle{grave over ( )} binary event). The LogHeaderType {grave over( )}header{grave over ( )} header consists of two [StringArrayType{grave over ( )}labels{grave over ( )}] handles cause.sub.-- handleLogArrayType {grave over ( )}records{grave over ( )} and effect.sub.--handle (in TimeType this order). {grave over ( )}achmowledge.sub.--time{grave over ( )} The records field PriorityType {grave over( )}priority{grave over ( )}. always has two elements, cause.sub.--value and effect.sub.-- value. RecordType is 0 for unary events, 1 forbinary active events, 2 for binary inactive events, and 3 for labelchange events. CompositeEventArray define structure An array ofCompositeEventArray = CompositeEventRecords {CompositeEventRecord {graveover ( )}record.sub.i {grave over ( )}}. PredicateOperator definePredicateOperatorType = Defines some SQL Type UnsignedType {grave over( )}operator{grave over ( )}. predicate operators 0 = AND 3 = OR 1 = IN4 = XOR 2 = BETWEEN PredicateOperand define PredicateOperandType = Apredicate for an SQL- Type Type {grave over ( )}operand{grave over ( )}type query is formed from a list of PredicateOperandType (seeSearchCriteria type). SortOrderType define structure UnsignedType {graveover ( )}order{grave over ( )} SortOrderType order is: StringType {graveover ( )}key{grave over ( )}. 0 = Ascending order 1 = Descending order.key names a key field of a table. SortOrderArray define structure.sub.--array SortOrderArray = {Sort OrderType {grave over ( )}order.sub.i{grave over ( )}}. SearchCriteria define structure SearchCriteria =Defines a query on a {PredicateOperandType LogSchemeRegister {grave over( )}operand.sub.i } The list of operands SortOrderArray {grave over( )}order{grave over ( )}. form a predicate in postfix (reverse Polish)notation. Type define union Type = All Types. /* type all types here */

[0148] Table 1 lists a set of methods which are presently defined forthe base class. All of these base class methods are inherited by theregisters and modules. TABLE 1 # Method Return-type Description 1read.sub.-- class( ) Class Type Causes a manager, module or register toreturn a number indicating what type of manager, module or register itis. 2 read.sub.-- name ( ) StringType Causes a manager, module orregister to return a string containing the name of the manager, moduleor register. 3 read.sub.-- label ( ) StringType Causes a manager, moduleor register to return a string containing the label for the manager,module or register. A label differs from a name in that it can beprogrammed by executing a Write Label method on the manager, module orregister. If no label is programmed the object name will be returned.128 write.sub.-- label(StringType) BooleanType Write the programmableobject label. If a null-string is written, the Label is destroyed. 129read.sub.-- security.sub.-- SecurityType Is executed to determinewhether a method can level(MethodType) be executed on a particularmanager, module or register. Not all methods are available on alldevices. The master device can determine whether it will receive a validresult by first executing this method. Another method, Read All SecurityLevels returns a list which corresponds to the security levels of allthe methods that can be executed on a manager or module. 130 read.sub.--all.sub.-- MethodSecurity Read the security levels for all methods of asecurity.sub.-- levels( ) ArrayType given object. Only methods valid forthe object's class are included. 131 read.sub.-- parent.sub.-- handleHandleType Returns a handle of the parent of a manager, module orregister. For instance, executing this method on an analog output modulewill return the handle of the analog output manager. Executing thismethod on the analog output manager will return a handle to the featuremanager. Executing this method on an analog output's output registerreturns the analog output module. 132 read.sub.-- owners( ) HandleArrayReturns a list of handles for all the modluels Type that own the objectthis method is executed on. This will include a list of modules if themethod is invoked on a register or a manager if it is invoked on amodule. 133 IsA(ClassType) BooleanType Returns a value indicatingwhether or not and object is derived from the class given as anargument. 134 check.sub.-- sanity( ) BooleanType Checks to see if themanager, module or Register is operating correctly. i.e., determineswhether the software that implements the object is operating correctly.Returns True if object is sane.

[0149] If a method invocation is unsuccessful, an ExceptionType will bereturned rather than the normal Return-type.

[0150] In the current implementation a module performs a function usingregisters. Input registers provide the information a module is operatingon. Setup registers permit modification of the operation of the module.Output registers contain the results of the module's operation. Theoutput registers of one module can be used as input registers foranother. The module keeps track of which registers are to be used forits input, output and setup. The links to the input registers can bemodified, but those to the output and setup registers are fixed. Amodule is said to “own” all the registers it is linked to. Methods mayalso be executed on registers once the handle to a register is known.The handle of a register or module is a number which is unique for eachregister and module on a device. When a method is invoked, a handle issupplied which indicates which module or register the method is to beinvoked upon.

[0151] In most instances, the methods that can be invoked on thedifferent types of registers depend on what type of register isinvolved. Table 2 lists a set of methods which are presently defined forall registers (all register classes are inherited from the registerclass). TABLE 2 Register Class (R) - class = 20 # Method Return-typeDescription 20 read.sub.-- time( ) TimeType Read the time of lastupdate. 21 read.sub.-- value( ) VoidType Read the value of the object 22write.sub.-- value(VoidType) BooleanType Write the value of the object

[0152] TABLES 3-19 list methods which are supported for the indicatedregister classes. (In Tables 3-19, “*” indicates that the method isinherited from the parent class and “+” indicates that the method isre-defined from the parent class.) TABLE 3 BooleanVariableRegister(BVR) - class = 21 This class defines a Boolean variable storagelocation. # Method Return-type Description 20 read.sub.-- time( )*TimeType Read the time of last update 21 read.sub.-- value( )+BooleanType Read the value of the register. 22 write. sub.--value(BooleanType)+ BooleanType Write the value of the register 30read.sub.-- ON.sub.-- label( ) StringType Read the ON label. 500write.sub.-- ON.sub.-- label(StringType) BooleanType Write the ON label.31 read.sub.-- OFF.sub.-- label( ) StringType Read the OFF label. 501write.sub.-- OFF.sub.-- label(StringType) BooleanType Write the OFFlabel. 32 read.sub.-- current.sub.-- state.sub.-- StringType Returns theON label if register value = label( ) True and OFF label if registervalue = False.

[0153] TABLE 4 EnumeratedRegister (ENR) - class = 22 This class definesa register that can store one instance of an enumerated list. # MethodReturn-type Description 20 read.sub.-- time( )* TimeType Read the timeof last update 21 read.sub.-- value( )+ StringType Read the value of theregister. 22 write.sub.-- value(StringType)+ BooleanType Write the valueof the register. The string must be one of the strings provided by theread.sub.-- unumerations( ) method - otherwise the method will fail. 520read.sub.-- enumerations( ) StringArrayType Read the enumeration list.This list contains ALL possible register values.

[0154] TABLE 5 NumericRegister (NR) - class = 24 This is the parentclass for Numeric Registers. # Method Return-type Description 20read.sub.-- time( )* TimeType Read the time of last update 21read.sub.-- value( )+ NumericType Read the value of the register 22write.sub.-- value(NumericType)+ Boolean Type Write the value of theregister

[0155] TABLE 6 NumericBoundedRegister (NBR) - class = 23 This defines anumeric value bounded by two values. # Method Return-type Description 20read.sub.-- time( )* TimeType Read the time of last update 21read.sub.-- value( )* NumericType Read the value of the register 22write.sub.-- value(NumericType)* BooleanType Write the value of theregister. If the value is outside the prescribed bounds, no value willbe written and an excepeition will be returned. 540 read.sub.-- bounds() NumeriArray Read the bounds of the register. The numeric Type arraywill have two elements. 541 write.sub.-- bounds(NumericArrayType)BooleanType Write the bounds of the register. The first array elementwill be the low bound and the second will be the hight bound.

[0156] TABLE 7 NumericVariableRegister (NVR) - class = 25 This defines anumeric storage location. # Method Return-type Description 20read.sub.-- time( )* TimeType Read the time of the last update 21read.sub.-- value( )* NumericType Read the value of the register 22write.sub.-- value(NumericType)* BooleanType Write the value of theregister

[0157] TABLE 8 DeltaRegister (DR) - class = 26 This defines adelta-function value. # Method Return-type Description 20 read.sub.--time( )* TimeType Read the time of last update 21 read.sub.-- value( )+VoidType Read the delta value 22 write.sub.-- value(VoidType)* BooleanType Output a delta-pulse

[0158] TABLE 9 Arrayregister (AR) - class = 27 This is the parent classfor all registers containing arrays. # Method Return-type Description 20read.sub.-- time( )* TimeType Read the time of last update 21read.sub.-- value(RangeType)+ VoidType Read a range of values. 22write.sub.-- value(IndexType, VoidType)+ BooleanType Write values atindex 35 read.sub.-- depth( ) SizeType Read the depthe of the array 36write.sub.-- depth(SizeType) BooleanType Write the depth of the array 37read.sub.-- rollover( ) UnsignedType Read rollover value - value is thehighest count that can be reached before rollover to 0.

[0159] TABLE 10 BooleanArrayRegister (BAR) - class = 28 This classdefines a non-circular array of Boolean values. # Method Return-typeDescription 20 read.sub.-- time( )* TimeType Read the time of lastupdate 21 read.sub.-- value(RangeType)+ BooleanArray Read a range ofType values. 22 write.sub.-- value(IndexType, BooleanType Write valuesat BooleanArrayType)+ index 35 read.sub.-- depth( )* SizeType Read thedepth of the array 36 write.sub.-- depth(SizeType)* BooleanType Writethe depth of the array 37 read.sub.-- rollover( )* UnsignedType Readrollover value.

[0160] TABLE 11 NumericArrayRegister (NAR) - class = 29 This classdefines a non-circular array of numeric values. # Method Return-typeDescription 20 read.sub.-- time( )* TimeType Read the time of lastupdate 21 read.sub.-- value(RangeType)+ NumericArray Read a range ofType values. 22 write.sub.-- value(IndexType, BooleanType Write valuesat NumericArrayType)+ index 35 read.sub.-- depth( )* SizeType Read thedepth of the array 36 write.sub.-- depth(SizeType)* BooleanType Writethe depth of the array 37 read.sub.-- rollover( )* UnsignedType Readrollover value.

[0161] TABLE 12 LogRegister (LR) - class = 30 This class defines acircular array of log-type structures. This class is intended for theimplenemtation of any kind of historic log. # Method Return-typeDescription 20 read.sub.-- time( )* TimeType Read the time of lastupdate 21 read.sub.-- value(RangeType)+ LogArrayType Read a range ofrecords. 22 write.sub.-- value(IndexType, BooleanType Write the recordsat index LogArrayType)+ 35 read.sub.-- depth( )+ BooleanTypeNotSupported 36 write.sub.-- depth( )+ BooleanType NotSupported 37read.sub.-- rollover( )* UnsignedType Read rollover value. 40read.sub.-- position( ) IndexType Read the present position. Note: Uponleaving the factory, the position = 0 (i.e. the first record will bewritten into position 0). The position always indicates where the nextrecord will be written. 41 write.sub.-- position(IndexType) BooleanTypeWrite the present position

[0162] TABLE 13 EventLogRegister (ELR) - class = 31 This class defines acircular array of event structures and a non-circular array of alarms.It is derived from the LogRegister class. The following methods aresupported. # Method Return-type Description 20 read.sub.-- time( )*TimeType Read the time of the last update 21 read.sub.--value(RangeType)* LogArrayType Read range of events 22 write.sub.--value(IndexType, BooleanType Write range of events LogArrayType)* 35read.sub.-- depth( )+ BooleanType NotSupported 36 write.sub.-- depth( )+BooleanType NotSupported 37 read.sub.-- rollover( )* UnsignedType Readrollover value. 40 read.sub.-- position( )* IndexType Read the presentposition. 41 write.sub.-- position(IndexType)* BooleanType Write thepresent position 45 read.sub.-- alarms( ) AlarmArrayType Read entirealarm array. 46 write.sub.-- alarms(AlarmArrayType) BooleanType Writeentire alarm array. 560 read.sub.-- alarm.sub.-- count.sub.-- rollover() UnsignedType Read rollover value of alarm counters in the AlarmArray -value is the highest count that can be reached before rollover to 0.

[0163] TABLE 14 SchemaRegister (DSR) - class = 39 This is derived fromTableRegister. A SchemaRegister loosely represents of a database schema,a collection of related database tables. In the current embodiment, thetables are not accessible via methods. These registers are usedprimarily as inputs to specialized modules that allow indirect access tothe tables. # Method Return-type Description 20 read.sub.-- time( )*TimeType Read the time of the last update. 21 read.sub.-- value( )+BooleanType NotSupported. 22 write.sub.-- value( )+ BooleanTypeNotSupported.

[0164] TABLE 15 Log View Register (LVR) - class = 40 The Log ViewRegister class is derived from Register. In database terminology, a viewis a database table that is derived from queries on other databasetables. Here a “view” is extended to mean a specialized representationof table or group of tables. A log View Register is used to access datastored in the Table Registers associated with the creator module (seeLog View Module). Data retrieved from the tables is reformatted andreturened as Composite Log Records. # Method Return-type Description 20read.sub.-- time( )* TimeType Read the time of the last update. 21read.sub.-- value(SearchCriteria)+. CompositeLogArray Returns allrecords that match SearchCriteria. 22 write.sub.-- value( )+ BooleanTypeNot supported. 583 read.sub.-- updates(SearchCriteria) CompositeLogArrayThe first time this method is invoked (for a particular program), allrecords that match the SearchCriteria are returned. Subsequently, onlythe newest matching records are returned.

[0165] TABLE 16 EventViewRegister (EVR) - class = 41 TheEventViewRegister class is a LogViewRegister that specializes the instorage of CompositeEventRecords. It also allows these records to bemarked as acknowledged and sends prioritized alarm messages toregistered clients. # Method Return-type Description 20 read.sub.--time( )* TimeType Read the time of the last update. 21 read.sub.--value(SearchCriteria)+ CompositeEventArray Returns all records thatmatch SearchCriteria. 22 write.sub.-- value( )* BooleanType Notsupported. 583 read.sub.-- updates(SearchCriteria)+ CompositeEventArraySee LogViewRegister 584 acknowledge(UnsignedArrayType) Boolean TypeMarks the specified event records as acknowledged. The argument is anarray of recordIDs.

[0166] TABLE 17 WaveformRegister (WR) - class = 32 This class defines anarray of points defining a waveform. # Method Return-type Descripiton 20read.sub.-- time( )* TimeType Read the time of last update 21read.sub.-- value( )+ WaveformType Read the present value of theregister 22 write.sub.-- value(WaveformType)+ BooleanType Write thepresent value of the register

[0167] TABLE 18 EventRegister (ER) - class = 33 This class defines aregister which holds an evet. # Method Return-type Description 20read.sub.-- time( )* TimeType Read the time of last update 21read.sub.-- value( )+ EventType Read the present value of the register22 write.sub.-- value(EventType)+ BooleanType Write the present value ofthe register

[0168] TABLE 19 TimeRegister (TR) - class = 34 This class defines aregister which holds unformatted time. # Method Return-type Description20 read.sub.-- time( )* TimeType Read the time of last update 21read.sub.-- value( )+ TimeType Read the present value of the register 22write.sub.-- value(TimeType)+ Boolean Write the present Type value ofthe register

[0169] It is also contemplated that a TableRegisterClass will bedefined. The TableRegisterClass represents a database table, rows ofdata organized into distinct columns. It is presently envisioned thatthe database tables will not be accessible using methods. Theseregisters may be used permanently as inputs to specialized modules thatallow indirect access to the tables.

[0170] Registers operate only as servers in the architecture. In otherwords they only respond to method invocations. Some of the most commonlyused registers in the preferred embodiment are boolean registers,enumerated registers, numeric registers and numeric bounded registers. Aflow chart for the server operation of a boolean register is shown inFIGS. 27A-27C. A flow chart for the server operation of an enumeratedregister is shown in FIGS. 28A-28B. A flow chart for the serveroperation of a numeric register is shown in FIGS. 29A-29B. A flow chartfor the server operation of a numeric bounded register is shown in FIGS.30A-30B.

[0171] It will be recognized by those skilled in the art that theregisters' functionality can be embedded within the modules.

[0172] The modules provide the IED the functionality in thearchitecture. FIG. 18 schematically illustrates a preferred embodimentof the properties of the modules. The modules can be considered as“black boxes” that read data at the inputs, manipulate the data in somefashion, and write the result to outputs. Input data is read fromregisters and output data is written to registers. For all types ofmodules, the links to input registers can be programmed, but the linksto output registers are fixed. Most modules have links to registerswhich contain setup information—these links are also fixed, and themodule can only read them. FIG. 19 illustrates the data flow for amodule. A module 861 is linked to input registers 863 a-863 n throughprogrammable links 869 a-869 n. Setup registers 867 a-867 n are linkedto module 861 through links 872 a-872 n which are not programmable.Output registers 864 a-864 n are linked to module 861 through links 870a-870 n which also are not programmable.

[0173] In the preferred embodiment, the modules have the followingproperties

[0174] An array of handles (input handles) point to the input registers.The module has shared ownership of these registers. The module reads aregister using the Read.sub.—Value method.

[0175] Module setup data (such as scaling information) is stored inregisters. An array of handles (setup handles) point to these Registers.There is one exception: For a manager module these Handles point toother modules rather than registers. The module has shared ownership ofthese objects.

[0176] The module uses the input data and setup data to produce outputdata according to the function of the module which is described by themodule behavior.

[0177] An array of handles (output handles) point to the outputregisters. The module has shared ownership of these registers. A modulewrites these registers using the Write.sub.—Value method.

[0178] UpdatePeriod contains the period at which the module updates theoutput registers.

[0179] ModuleSecurity contains the security level which the module useswhen invoking methods on other objects.

[0180] The module has a class which is unique to that type of module.(e.g. All setpoint modules would have the same class).

[0181] The module has a name. This name is fixed (read only) and isdifferent in every module.

[0182] The module has a label which can be programmed.

[0183] A method security level is defined for every method which can beinvoked on a module. Thus, there is a security parameter for everymethod which can be invoked on the module.

[0184] The module has owners which are listed in an array of Handles.This array lists all the module(s) that have shared ownership of themodule.

[0185] A module is created by a manager using the Create.sub.—Module( )method. When the module is created all output registers and setupregisters are also created. However, input registers are not createdwhen a module is created. Often, a manager will have a fixed number ofmodules and the Create.sub.—Module( ) method will not be supported.

[0186] The module class (class=500) is derived from the base class. Themethods listed below in Table 20 are common to all module classes (allmodule classes are inherited from this module class). TABLE 20 # MethodReturn-type Description 1000 read.sub.-- input.sub.-- handles( )HandleArray Returns a list of the handles to the Type registers that areconnected as inputs to the manager or module. (In the currentembodiment, managers do not have inputs.) 1001 write.sub.-- input.sub.--handles(HandleArrayType) BooleanType Accepts a list of handles andattempts to link a module or manager to these input registers. (In thecurrent embodiment, managers do not have inputs.) The handle order isdefined in the module definitions. If one of the handles is incorrectthe method will fail and NO handles will be written (i.e. all ornothing). 1002 read.sub.-- input.sub.-- classes( ) ArrayUnsigned Readsthe allowed register classes for the ArrayType write.sub.-- input.sub.--handles method. The returned array has the same number of elements asthe HandleArray used in the write.sub.-- input.sub.-- handles method. Ifthe returned array has an element that contains a Null rather than aclass this indicates that this input element cannot be programmed. 1003read.sub.-- output.sub.-- handles( ) HandleArray Returns a list ofhandles to the output Type registers of a module or manager. (In thecurrent embodiment, managers do not have outputs.) The handle order isdefined in the module definitions. 1004 read.sub.-- setup.sub.--handles( ) HandleArray Returns a list of handles to the setup Typeregister of a module or a list of handles to modules for a manager. Thehandle order is defined in the module definitions. 80 read.sub.--setup.sub.-- counter( ) CounterType Returns a number indicating how manytimes the module or manager has had its configuration changed. A masterdevice can keep a local copy of this number. If another master devicechanges the setup of the slave device, the first manager can detect thechange by comparing its count with the current count. 81 read.sub.--update.sub.-- counter( ) CounterType Returns a number indicating howmany times the module or manager has successfully invoked a method towrite a new value to its output registers. A master device can thendetermine if it is necessary to read the output from the module ormanager. (In the current embodiment, managers have no outputs.) 1005read.sub.-- update.sub.-- period( ) StringType Returns a numberindicating the minimum amount of time there will between the module ormanager updating its output registers. (In the current embodiment,managers have no outputs.) Typical response is one of: “one cycle” “onesecond” “two cycles” 1006 read.sub.-- module.sub.-- security( )SecurityType Returns a numbers indicating the security access a modulehas. Other modules or registers may refuse to execute a method invokedby a module which does not have a high enough security level.

[0187] Table 21 below lists the behavior details for the moduleparameters. TABLE 21 Module Parameter Behavior update.sub.-- counterwill be incremented every time a write.sub.-- value( ) method issuccessfully invoked on one of the registers identified by the outputhandles. Note: by default the update counter will be incre- mented everytime an module writes an event register. setup.sub.-- counter will beincremented every time a write.sub.-- value( ) method is successfullyinvoked on one of the sys- tem registers identified by the setup handlesand every time the write.sub.-- input.sub.-- handles( ) method issuccessfully invoked.

[0188] Table 22 below provides a list of the modules (including thecorresponding input, output and setup registers) presently supported bythe presently preferred embodiment. TABLE 22 # Module Name InputRegisters Output Registers Setup Registers Module Description 501 PowerMeter V1 (NAR) Vabc*(NVR).sup.1 ode(ENR) Basic 3-phase power met V2(NAR) Vllabc*(NVR) PT Pri Volts(NBR) met meter. V3 (NAR) labc*(NVR) PTSec Volts(NBR) PhaseOrder: l1 (NAR) KWabc*(NVR) CT Pri (NMR) “ABC” l2(NAR) KVARabc*(NVR) CT Sec l(NBR) “ACB” l3 (NAR) KVAabe*(NVR) 14 CT Pril(NBR) NormFreq: l4 (NAR) PFSIGNabc*(NVR) 14 CT Sec l(NBR) “50”PFLEADabc*(NVR) l1 Polarity(ENR) “60” PFLAGabc*) NVR) l2 Polarity(ENR)“400” Vunbal(NVR) l3 Polarity(ENR) PhaseLabels: lunbal(NVR)PhaseOrder(ENR) “ABC” l4(NVR) NormFreq(ENR) “RST” Iresidual(NVR)PhaseLabels “XYZ” PhaseRev(BVR) (ENR) “RYB” LineFreq(NVR) Event(ER) 502Analog Input ScaledAnalog(NVR) Zero Scale(NBR) Analog Input function.Event(ER) Full Scale(NBR) Port indicates H/W Input Port(ENR) port. 503Analog Output Source(NVR) State(NVR) Zero Scale(NBR) Analog Outputfunction. Event(ER) Full Scale(NBR) OutputState gives present OutputModeoutput value as a % of (ENR) output full scale. Port(ENR) OutputMode:“0-20 ma” “4-20 ma” note: OutputMode is not supported for all devices.Port indicates H/W output port. 504 Digital Input State(BVR) InputMode(ENR) Processes raw digital Trigger(DR) EvLogMode signals received fromH/W Event(ER) (ENR) digital input channel. InPolarity(ENR) Trigger onvalid state Debounce(NBR) changes. Port(ENR) InputMode: “Pulse” “KYZ”EvLogMode: “Log Off” “Log On” InPolarity: “non-inverting” “inverting”Debounce in ms. Port indicates H/W input port. 505 Digital OutputSource(BVR) State(BVR) EvLogMode Provides raw bit pattern ForceOn(DR)Mode(BVR) (ENR) for H/W digital output ForceOff(DR) Event(ER)OutPolarity(ENR) channel. Normal(DR) PulseWidth(NBR) EvLogMode:Port(ENR) “Log Off” “Log On” OutPolarity: “non-inverting” “inverting”PulseWidth: 0 = continuous output. not 0 = pulse width in ms. Portindicates H/W output port. 506 Pulser Source(DR) Event(ER)PulseWidth(NBR) Proves pulse output (e.g. OutputMode for Kwh pulsing).Output (ENR) Port is pulsed every time OutPolarity(ENR) a pulse isreceived at the Port(ENR) Source input. PulseWidth specified in ms.OutputMode: “Pulse” “KYZ” OutPolarity: “non-inverting” “inverting” Portindicates H/W output port. 508 SWD Source(NVR) SWD(NVR) Period(NBR)Provides SWD on source Sync(DR) Prediction(NVR) #Periods(NBR) input.Reset(DR) Event(ER) SyncMode(ENR) Period in minutes. PredictSpeedSyncMode: (NBR) “internal” “external” Sync input is used in externalsync mode, otherwise un-used. PredictSpeed from 0-99 (99 = fastresponse). 509 TD Source(NVR) TD(NVR) Period(NBR) Provides ThermalDemand Reset(DR) Event(ER) TimeConstant calculation on a single (NBR)source input. Period in minutes. TimeConstant is a percentage of thePeriod. 510 Integrator Integrand(NVR) Result(NVR) Divisor(NBR) Providesintegration Enable(BVR) Pulse(DR) IntMode(ENR) function. Reset(DR)Event(ER) PulseSize(NBR) Enable allows gating Divisor in seconds (forKwh the Divisor would be 3600) IntMode: “forward” “reverse” “absolute”“net” The Pulse output will be pulsed when the Result output changes bythe amount specified in PulseSize setup . . . 511 Min Source(NVR)Min(NVR) Event(ER) Scans Source register for Enable(BVR) Trigger(DR) newminimum values. Reset(DR) Enable allows gating for every new minimum theMin and Trigger registers are updated. 512 Max Source(NVR) Max(NVR)Scans Source register for Enable(BVR) Trigger(DR) Event(ER) new maximumvalues. Reset(DR) Enable allows gating for every new maximum the Max andTrigger registers are updated. 513 Setpoint Source(NVR/BVR) Status(BVR)HiLim(NBR) Provides hysteric Enable(BVR) Trigger(DR) LoLim(NBR) setpointfunction on Reset(DR) Event(ER) TDOperate(NBR) numberic of looleanvalue. TDRelease(NBR) Enable allows gating. InputMode(ENR) Trigger onsetpoint going EvaluateMode ACTIVE. (ENR) TDOperate and TDReleaseEventPri(NBR) in ms. InputMode: “Signed” “Absolute” EvaluateMode:“GreaterThan” “LessThan” 514 FFT Source(NAR) FFT(NAR) Performs FFTcalculations Enable(BVR) Event(ER) on input source array and generatesan array of complex numbers. 515 Harmonics Source(NAR) HD1(NVR) Performsharmonics Analyzer Enable(BVR) . . . HDN(NVR) calculations on an N-sizeTHD(NVR) array of complex numbers TEHD(NVR) (i.e. from an FFT module).TOHD(NVR) KFactor(NVR) Event(ER) 516 Recorder Source1 RecLog(LR)Depth(NBR) Provides a snapshot of the (NVR/BVR/NAR/ Event(ER)RecMode(ENR) input source registers BAR/WR) EvLogMode when triggerregister is . . . SourceN (ENR) pulsed. Can record (NVR/BVR/NAR/waveforms, arrays, and BAR/WR) single value registers. Enable(BVR)Enable allows gating Trigger(DR) RecMode: “Circular” “Stop-when-full”EvLogMode: “Log Off” “Log On”. 517 Wave form RawWF(NAR/BAR)FormattedWF(WR) Format(ENR) Formats waveform data. Formatter Event(ER)Format (#sampls/cyc x #cycles) “128.times.12” “64.times.28” etc . . .518 Periodic Enable(BVR) Trigger(DR) Period(NBR) Pulses the Triggeroutput Timer Initialize(DR) Event(ER) TimingMode whenever the timervalue (ENR) reaches zero. ResetMode(ENR) Period in ms. TimingMode: “Syncto UNIX” “Sync to Init” ResetMode: “init to Period” “init to zero” 519One-shot Enable(BVR) State(BVR) Period(NBR) Provides a one-shot timer.Timer TriggerIn(DR) TriggerOut(DR) State: Event(ER) 1 when timer isrunning 0 after time out The Trigger Out activates at the end of thetiming interval. Period in ms. 520 Counter Trigger(DR) Count(NVR)Multiplier(NBR) Increment/Decrement Initialize(DR) Event(ER) UpDown(ENR)Count register by the amount specified in the Multiplier register eachtime the counter is triggered. UpDown: “Count Down” “Count Up” 521LogicalAndOr Source1(BVR) Results(BVR) Mode(ENR) Performs either Logical. . . SourceN(BVR) Event(ER) EvLogMode AND, NAND or function on (ENR)the source inputs. Mode: “AND” “NAND” “OR” EvLogMode: “Log Off” “Log On”522 Event Log Event1(ER) EventLog(ELR) EvLogDepth Logs all event recordsin Controller . . . EventN(ER) (NBR) EventLog regardless ofAlarmPriority priority. (NBR) Keeps track of previous and presentlyactive alarms in EventLog. Any event with a priority equal to or aboveAlarmPriority is an alarm. 528 LogSchema LogInout1 (LR) LogSchema(DSR)Uploads log records from . . . LogInputN (LR) the remote LogRegisterinputs and stores them in a database schema. 529 EventSchema EventInput1(ELR) EventSchema(DSR) Combines event records . . . EventInputN (ELR)and alarm information from each IED and stores the data in a databaseschema. 532 Label EventLog1 (ELR) LableTable (DTR) Maintains a historiclist of . . . EventLogN (ELR) all labels that exist on each IED. Theremote EventLogRegister inputs can be used to track label changes.Initially all labels are read by accessing the feature manager. 533LogView LogSchema (DSR) LogView (LVR) Acts as a bridge betweenLabelTable (DTR) the input database tables and the outputLogViewRegister. The input tables are joined to produce detaild logrecords. 534 EventView EventSchema (DSR) EventView (EVR) Acts as abridge between LabelTable (DTR) the input database tables and the outputEventViewRegister. The input tables are combined to produce detailedevent records. 524 Comm Reset (DR) Event (ER) CommMode CommunicationsInterface. (ENR) CommMode: Baudrate(ENR) “RS232” HandshakeMode “RS485”(ENR) BaudRate: RTSLevel(ENR) “300” CTSLevel(ENR) “1200” RTSDelay(NBR)etc . . . UnitD(NBR) HandshakeMode: “RTS with level” “CTS with level”RTSLevel: “active low” “active high” CTSLevel: “active low” “activehigh” RTSDelay: specifies transmission delay time (in ms) after RTS hasbeen raised. 523 Data Acquisition Output1(NAR) Provides sampled data . .. OutputN(NAR) from the waveforms of a power system. 530 ExternalControl Numeric1(NVR) Provides registers that can . . . NumericN(NVR) becontrolled externally. Trigger1(DR) . . . TriggerN(DR) Switch1(BVR) . .. SwitchN(BVR) 525 Diagnostics Reset(DR) Output1(BVR/NVR) Outputregisters provide . . . OutputN(BVR/NVR) diagnostic features . . .Event(ER) 526 Real-time Clock Time(TR) Provides real-time clockfacility. Time register in universal (GMT) seconds. 527 FactoryEvent(ER) Setup1 Used for Factory (ENR/NBR) Purposes. . . . SetupN Allother uses violate the (ENR/NBR) architecture. It has no owner andcannot be created or dewtroyed (“it merely exists”) It can be accessedonly with the factory security level. 531 Symmetrical Source1(NAR)ZeroSeqMag(NVR) Harmonic(NBR) Calculates the magnitude ComponentsSource2(NAR) ZeroSeqPhase(NVR) and phase for each Source3(NAR)PosSeqMag(NVR) sequence component for a Enable(BVR) PosSeqPhase(NVR)particular harmonic. NegSeqMag(NVR) Typically, FFT Modules isNeqSeqPhase(NVR) used to produce the Event(ER) Numeric Array Registersinputs.

[0189] In the following description reference is made to “managers”. Itwill be noted that managers are just a specific type of module whichhave additional functionality. The purpose of the managers is to managemodules. One manager is needed for each practical group of modules, suchas setpoint modules and min modules.

[0190] Table 23 below provides a list of the methods which are addedspecifically for the manager class. (All class and module class methodsare inherited by the manager class but are not shown here for reasons ofbrevity.) TABLE 23 # Method Return-type Description 100 read.sub.--module.sub.-- setups.sub.-- counter( ) CounterType Returns a numberindicating how many times the setup registers of the modules below amanager have been changed. The master device can keep a local count ofthis number in order to determine if another master device hassuccessfully invoked a method to change the setup of the device. Forinstance, if a master device keeps this count for the feature manager,it can tell if any setup register on the deivce has been changed withoutgoing to each individual module. 101 read.sub.-- module.sub.--updates.sub.-- CounterType Returns a number indicating how many timescounter( ) the output registers of the modules and managers beneath acertain manager have been updated. Used in the same fashion as ReadModule Setups Counter, the Read Module Updates Counter is used todetermine if any of the modules beneath the manager have successfullyinvoked a method to update their output registers. (In the currentembodiment, managers have no outputs.) 1500 create.sub.-- module(ClassType) HandleType Creates a module and stores the module handle in thesetup handles array; return handle to module. The method read.sub.--managed.sub.-- class indicates which class of module can be created.1501 destroy.sub.-- module(HandleType) BooleanType Destroys a module.Handle must be one of setup handles or an exception will be returned andthe method will fail. The resources for that module are then availableto perform other functions on the device. 1502 read.sub.--managed.sub.-- class( ) ClassType Returns the class of module which canbe created with the create.sub.-- module method.

[0191] Every system has a “root” manager module called the featuremanager. The feature manager has setup handles to all the othermanagers. Importantly, the feature manager handle is identical for allsystems. The handle for the feature manager is 2. Starting with thishandle, it is possible to determine the entire system configuration.

[0192] As was mentioned previously, modules act as both clients andservers in the object oriented architecture. In the present embodiment,the client and server portion of the modules operate separately. Theserver portion of the modules respond to method invocations. The serverportion follows the same logic for all modules (except the managers) onthe device. A flow chart of the logic for the server portion of a moduleis shown in FIGS. 19a-19 c.

[0193] A description is now given of how the modules described above areused in the system of FIGS. 8-10. In the preferred embodiment the outputregisters from the data acquisition module 952 (FIG. 11) (which aredigital signals representing the samples of the voltage and current) arepermanently connected as input registers 120 of a module called thepower meter module 926 (FIG. 12). Conceptually, the data acquisitionmodule encompasses signal conditioning circuitry 860, 862, 864, 866A,866B, 866C, 868A, 868B, 868C, 870, the A/D converters 829, 830 andsoftware in the DSP 828. The interface between the data acquisitionmodule and the power meter module includes the dual port RAM 827. A flowchart for the logic of the client portion of the data acquisition module952 is shown in FIG. 11A. The power meter module 926 owns setupregisters 922 which modify the operation of the power meter module 926and output registers 924 which contain the results of the calculationsthat the power meter module does and can be connected to other modules.A flow chart of the logic for the power meter module 926 is shown inFIGS. 12A-12L.

[0194] The module called the analog input module is an example of amodule which connects to a physical signal in a different way. Apreferred embodiment of the analog input module 928 is illustratedschematically in FIG. 13. An exemplary embodiment of the logic for theclient portion of the analog input module of FIG. 13 is illustrated inflowchart form in FIG. 13A. The analog input module 928 owns a portsetup register 930 which defines which of the auxiliary input signals820 the module is associated with. Analog input modules can also beconnected to digital I/O signals 844 (FIG. 9). In this configuration,the Digital I/O transceiver 849 operates in input mode and the analoginput module converts the frequency of the digital signal into a number.In this embodiment, an external voltage to frequency converter isconnected to the digital input signal line.

[0195] Analog output modules can also be connected to the Digital I/OSignals 844. In this configuration, an external device is connected tothe I/O line which converts the digital signals coming from the analogoutput module 930 to an analog signal. A preferred embodiment of theanalog output module 930 is illustrated schematically in FIG. 14. Anexemplary embodiment of the logic for the client portion of the analogoutput module 930 is illustrated in FIG. 14A in flowchart form.

[0196] The digital input module 940 transforms a digital I/O signal 844into a form that can be used as an input to other modules. A preferredembodiment of the digital input module 940 is illustrated schematicallyin FIG. 15. An exemplary embodiment of the logic for the client portionof the digital input module 940 is illustrated in FIGS. 15A-15B inflowchart form.

[0197] The digital output module 950 transforms the output from anothermodule into a signal on a digital I/O signal line 8. A preferredembodiment of the digital output module 950 is illustrated schematicallyin FIG. 16. An exemplary embodiment of the logic for the client portionof the digital output module 950 is illustrated in FIGS. 16A-16H inflowchart form.

[0198] Additional modules that operate only on the results of othermodules are also possible. An example of one of these modules is theAND/OR module 960 illustrated schematically in FIG. 20. The AND/ORmodule 960 takes a number of boolean variable register inputs andperforms a logical AND or OR on them to create a result. The CalcModesetup register 961 determines which AND or OR function is beingexecuted. The EvLogMode setup register 962 determines whether eventswill be generated in the Event output register 963 when the Result 964register changes. The logic for a preferred embodiment of the clientportion of the AND/OR module 960 is illustrated in FIGS. 20A-20B inflowchart form. The setpoint module 972 is shown schematically in FIG.21. The logic for a preferred embodiment of the client portion of thesetpoint module 972 is shown in FIGS. 21A-21C. These modules do notinterface to the outside world.

[0199] Another module of note is the EventLog module 970. The EventLogmodule is shown schematically in FIG. 22. A flowchart of a preferredembodiment for the client portion of the EventLog module is shown inFIG. 22A. Nearly all other modules within the device are connected to anevent output register. When an unusual state arises within a module, itmay send an event message to the event register. The EventLog module 970takes event registers as an input and invokes a method to write the“event” into its event log output register. The result is that the EventLog register then contains a list of all the significant occurrencesthat have happened on the device. In this manner, the time as well asthe effects which occur in the IED may be recorded.

[0200] An example of the events that may be generated on the power meterof the present embodiments can be seen in Table 24. TABLE 24 Event #Time Cause Label Cause Value Effect Label Effect Value 1 Dec. 15/94 @800 None External Motor 4 Powdered Down 2 Dec. 15/94 @ 800 Motor 4Powdered Down Cooler 7 Shutdown 3 Dec. 15/94 @ 923 kW Phase A 1000 OverkWa True 4 Dec. 15/94 @ 923 Over kWa True Relay 6 Closed

[0201] In table 24 a number of events in the system are shown. Event #1is an event that a digital input module might create if its hardwarechanged state. In this case, the digital input is connected to thestatus output of a motor. There is no cause label in this case since thecause is external to the meter. Event #2 shows an event that a digitaloutput module might create. The source input of this digital outputmodule is connected as the state output of the digital input module.Event #3 is an event that a setpoint module might create. The setpointmodule has detected that the amount of power being consumed is too greatso its status output register is set to true. This status outputregister is connected as the source input register to another digitaloutput module. In Event #4 the digital output module is shown to close arelay. Therefore, the fact that kW Phase A has exceeded a certain boundshas caused an external relay to close (hopefully rectifying theproblem).

[0202] A significant feature of the disclosed architecture is that themodules can be linked in arbitrary fashions to form arbitrary functionalblocks comprised of networked objects.

[0203] An example application using the architecture of this embodimentsis shown in FIG. 23. In this example, a setpoint module 972 is used tomonitor Phase A current from the power meter module 926. The setpoint isenabled using a digital input module 940 which is driven by the manualswitch 941. The setpoint setup registers are configured so that thesetpoint goes ON when the current exceeds 100 Amps. The setpoint statusoutput controls the digital output module 950, which drives a relay 951which could control a motor (not shown). Whenever the phase A currentexceeds 100 Amps and the manual switch 941 is closed, the relay 951 willbe closed causing the motor to turn off. (Note: in this example setupregisters and other registers that are not needed for the example arenot shown.) It will be appreciated by those skilled in the art that thenumber and variety of possible additional modules and applications isunlimited.

[0204] The operation of most of the modules in the IED is governed bythe client portion of the module flow controller. A flow chart for theexecution of the client portion of the module flow controller is shownin FIG. 24A. The module flow controller causes different modules withinthe device to execute. The module flow controller only triggers modulesto execute that have valid input registers. Therefore, any modules thatdo not meet this requirement do not use any of the processing poweravailable to the device. The server portion of the module flowcontroller is executed when a module has the write input handles methodinvoked on it. A flow chart for the operation of the server portion ofthe module flow controller is shown in FIG. 24B. The server portion ofthe module flow controller records whether the input handles beingwritten are valid or not. The client portion then uses this informationwhen it makes its decision on whether to execute the module or not.

[0205]FIG. 25 schematically illustrates a preferred embodiment of amanager, the analog output manager 1100. A flow chart for the logic forthe server portion of a manager is shown in FIGS. 25A-25B. In thepresent embodiment, managers have no client portion. There is oneresource manager 1100 for each type of module. Each resource manager1100 may have many modules below it.

[0206] Every manager 1100 in an IED resides beneath the feature managerfor the device. A preferred embodiment of feature manager 1200 isschematically shown in FIG. 26. A flow chart for the logic of the serverportion of the feature manager is show in FIGS. 26A-26B. All themanagers on the device appear as setup registers 1201 to the featuremanager 1200. The feature manager 1200 controls access to the entiredevice 900. Starting from the feature manager 1200, a master device,such as PC 914, can determine all input, output and setup registers forevery module on the IED device 900.

[0207] Each manager is said to own all the modules that appear as itssetup registers. The feature manager is said to own the resourcemanagers that appear as setup registers to it. Therefore, a hierarchy ofmodules exists with the feature manager on top.

[0208] In order for a master device, such as PC 914, to access theinformation in a slave device, such as the IED 900, it invokes methodson the managers, modules or registers. In order for a master to executea method on a slave, it must have a handle. The handle indicates whichmanager, module or register the method is to be acted on. For example,the handle for the feature manager for any type of slave device is 2 inthe current embodiment. This is the only thing that is fixed in thearchitecture and every type of device has a feature manager with ahandle of 2. From this handle, the entire configuration of the devicecan be determined.

[0209] With the configuration of the present embodiments, the slavedevice, such as the IED's 900 may have the capability to execute manydifferent objects, but only a limited number of objects can be executedat any one time due to processing power constraints. The flow controlclient controls the operation of modules. Therefore, only the modulesthat have valid input, output and setup registers connected to them areexecuted.

[0210] In order for a master device, such as a PC 914, to determine theconfiguration of a slave device without the master device having anyprevious knowledge of the configuration, the master device invokescertain methods on the feature manager. These methods are fixed in thearchitecture. In other words, every feature manager for every differenttype of slave device will interpret these methods in the same way. Forinstance, the master device may invoke the method Read Setup Handles onthe feature manager which requests a list of the managers that residebeneath it. From this list, the master device can then go to eachindividual manager and request the operating modules beneath them byagain executing the method Read Setup Handles. Once the master deviceknows which modules are operating, it can request of each module itscurrently connected input, output and setup registers using theappropriate methods and thus determine the entire configuration of thedevice. Thus, without any prior knowledge of the slave device, or itsconfiguration, the master device can determine all characteristics ofthe device. The master device can then invoke other methods to changethe configuration of the device. The slave devices, however can operateautonomously without the involvement of the master devices.

[0211] Thus, the slave devices, such as power monitors, can be readilyconfigured to exactly match a user's unique requirements and to providethe ability to do so without interrupting the operation of the rest ofthe functions the device is performing. The slave devices, such as theIEDs, can be networked to one or more computers and the slave devicescan be configured or reconfigured via the communications network.

[0212] Further, with the present embodiments, it is not necessary tochange the software on a master device when a slave device is upgraded.

[0213] The modules are independent or autonomous. Thus, when a module ismodified, there is no need to modify the other modules. As used hereinthe term “independent modules” means that modifications or changes canbe made to one or more modules without a need to modify the remainingmodules (i.e. a modification to one module has no effect on theoperation or functionality of the other modules.

[0214] The feature manager keeps a count of how many times theconfiguration of the device has been changed. A master can invoke a themethod Read Module setups counter on the feature manager to request thiscount. If there are multiple masters changing the configuration of thedevice, each master need only request this count from the featuremanager to determine if the configuration of the device has beenchanged.

[0215] The feature manager also contains a count of how many times themodules below it have updated their output registers. Each individualmanager has a count of how many times the modules below it have updatedtheir output registers and each individual module has a count as well.Therefore, if a master device executes the method Read Module UpdatesCounter and finds that none of the modules under a certain manager haveupdated their output registers since the last time the master read thevalues in the registers, the master does not need to wastecommunications bandwidth reading the same values again.

[0216] Methods and Modules are preferably assigned a security level.This permits the system to be configured such that certain users haveaccess to all of the system functions while other users have access toonly selected functions.

[0217] The Read Security Level, Read All Security Levels and Read ModuleSecurity methods can be used to determine what level of authorization isnecessary to access the various methods and modules in the system.

[0218] The foregoing description of the preferred embodiments of thepresent embodiments has been presented for purposes of illustration anddescription. The described embodiments are not intended to be exhaustiveor to limit the embodiments to the precise forms disclosed. Obviouslymany modifications and variations are possible in light of the aboveteachings. The embodiments which were described were chosen in order tobest explain the principles of the embodiments and its practicalapplications. It is intended that the scope of the embodiments bedefined by the following claims, including all equivalents.

[0219] Referring back to FIG. 3 is a diagram using the object-orientedarchitecture disclosed in the copending application Ser. No. 08/369,849,now U.S. Pat. No. 5,650,936. The diagram of FIG. 3 shows modules whichrepresent program objects. A “module” may be regarded to be an activeobject in the program architecture. Modules behave as both a client anda server. The client portion of a module contains the active componentswhich perform the various tasks within the device. Modules act as “blackboxes” that read data in at the inputs, manipulate the data in somefashion, and write the result to outputs. The inputs are read fromregisters and the outputs are written to registers.

[0220] The diagram of FIG. 3 shows a functional relationship between theprogram objects that may be used in a preferred embodiment of thesystem. The objects shown in FIG. 3 include objects that may bephysically located (or that may be regarded as “running”) on the phasortransducers and/or the phasor array processors, or both. In a preferredembodiment, the modules shown in FIG. 3 are located on a single phasortransducer, such as the phasor transducer 51. The other phasor modules,50, 52, 53, and 54, would include similar phasor modules.

[0221] (1). Phasor Power Modules

[0222] As shown in FIG. 3, running on the phasor transducer 51(specifically on the phasor transducer local microprocessor 100) are aplurality of phasor modules 200. In the embodiment shown, the pluralityof phasor modules 200 includes a phasor module for each voltage andcurrent channel. The plurality of phasor modules 200 receive thedigitized values of the voltage and current signals V1, V2, V3, I1, I2,I3, and I4, that are output from the analog to digital converter 70 inFIG. 2. (Each of the other phasor transducers 50, 52, 53, and 54 of FIG.1 would likewise include its own plurality of phasor modules for thedigitized values of the voltage and currents channels sensed by itscorresponding voltage and current sensors associated with itscorresponding circuit.) In the embodiment shown in FIG. 3, the plurality200 of phasor modules includes seven phasor modules, 200A-200G. Each ofthese phasor modules receives as an input one of the digitized voltageor current signals, V1, V2, V3, I1, I2, I3, and I4. In addition, each ofthese modules includes an “enable” input, such as input 202A on module200A. The “enable” input enables operation of the module. The “enable”input is received from another module with a Boolean output. In analternative embodiment, the module 200A may defaulted to “enable” andwill provide an output unless a negative signal is received on its“enable” input.

[0223] Each of the phasor modules 200 provides an output in the form ofa phasor array output register and an event register. For example,phasor modules 200A-200G output phasor array output registers 206A-206G,respectively, and event registers 208A-208G, respectively. Each of thephasor module output registers 206 contains an array of phasors computedby its respective phasor module that represents its respective digitizedinput voltage or current for each harmonic for which the module isenabled. Each phasor array register and each event register also includea time stamp that indicates the instant in time that it represents.

[0224] (The “phasor” may be a polar number, the absolute value ormodulus of which corresponds to either the peak magnitude or the RMSvalue of the quantity, and the phase argument to the phase angle at zerotime. Alternatively, the “phasor” may be a complex number having realand imaginary components values, or the phasor may use rectangular orexponential notation. Phasors may be used to represent the voltage,current, power, or energy in a phase conductor, in an electric circuit,or in group of circuits. By contrast, conventional sensing devicesgenerally measure only “power parameters.” A “power parameter” may beregarded as a scalar representation of a voltage, current, power,frequency, etc., in the line. A “phasor array” may be an array or matrixof phasors. Phasor arrays may be used to represent the voltage, current,power, or energy phasors in the phase conductor, or circuit, or group ofcircuits, being sensed. Each element of the phasor array represents thephasor for a particular harmonic in a phase conductor voltage, power orenergy signal. The array may be a single element array consisting of asingle phasor for a single harmonic or the fundamental frequency.)

[0225] As mentioned above, each of the phasor modules also includes anevent register, such as event register 208A-208G. An “event” may beregarded as any occurrence in the system that warrants logging and thedata in the event registers 208 identify the nature of the event. Thedata in the event register 208 uniquely identifies the type of event andthe time the event occurred.

[0226] As mentioned above, in one embodiment, the plurality of phasormodules 200 and their output registers 206 and 208 are included asprogram objects on the local microprocessor 100 in the phasor transducer51 associated with the voltage and current lines 15A, 15B, and 15C, thephasors of which are being computed. However, in alternativeembodiments, the plurality of phasor modules 200 and their outputregisters 206 may be included as program objects on a microprocessorthat is physically located remotely in one or more of the phasor arrayprocessors, such as the phasor array processors 130, 131, and 132, oreven on a microprocessor located on another of the phasor transducers,such as the phasor transducers 50, 52, 53, or 54. The program objectsthat perform the functions of the phasor modules 200 are not necessarilyrestricted to a specific physical location. If the program objects thatperform the functions of the phasor modules are not physically locatedin the phasor transducer associated with the voltage and current linesthe phasors of which are being computed by the modules, then thedigitized outputs of the analog to digital converter may be transmittedover the network to another microprocessor where the phasor modules maybe located.

[0227] As mentioned above, the values included in the phasor arrayoutput registers 206 represent the phasor values computed by each of thephasor modules 200 for each harmonic that is enabled. There are severalmethods that can be used to compute these phasor array values. Onepreferred method is to use a fast fourier transform to compute thephasor value for each harmonic frequency from the digitally-sampleddata.

[0228] Each of the modules 200 includes scaling and notation setupparameters that may be used to configure the output format and scaling.For example, the modules 200 may be configured in various modes, e.g.wye or delta, and the phasor notation may be provided in polar,rectangular, complex, or exponential notation. In addition, the scalingparameters may be set to provide for selection of units, percent,primary, secondary, per unit (PU), or Engineering units. In addition,there may be setup parameters used to select the harmonics that areenabled in the module.

[0229] (2). Phasor Power Meter Module

[0230] The phasor values in the phasor array output registers 207A-207Gare provided as inputs to a phasor power meter module 220. Like thephasor modules 200, the phasor power meter module 220 is preferablyimplemented as a program object on the phasor transducer localmicroprocessor 100. The phasor power meter module 220 computes thephasor product of the voltage phasor arrays and the current phasorarrays for each phase in turn to generate the power phasor array foreach phase. Also, the phasor power meter module 220 computes the sum ofthe power phasor arrays for all the phases to generate the total real,reactive, and apparent power parameters for all the harmonics that areenabled. An important function of the phasor power meter module 220 isthe ability to buffer and time align the phasor array data from all theinputs so that the power calculation uses data which are representativeof the same instant in time. The phasor power meter module 220 alsoincludes an “enable” input 221 that enables the operation of the phasorpower meter module 220.

[0231] The phasor power meter module 220 provides an output in the formof power meter output registers 226. The power meter output registers226 include the following registers: (1) register 226A-226C that includea power phasor array for each phase, representing the real and reactivepower for that phase for each harmonic that is enabled, (2) a register226D that includes a total power phasor array representing the threephase total real and reactive power for each harmonic that is enabled,(3) a 226E register that includes a total real power parameter, (4) aregister 226F that includes a total reactive power parameter, (5) aregister 226G that includes a total apparent power parameter, and (6) anevent register 226H.

[0232] The phasor power meter module 220 may be configurable to providefor selection of appropriate parameters for both its inputs and itsoutputs. For example, the phasor power meter module 220 may beconfigurable to provide its phasor output in various notations, such aspolar, rectangular, complex, or exponential. The phasor power metermodule 220 may be configured for scale, e.g. per unit, percent, orEngineering units. The phasor power meter module 200 may also beconfigurable for the number of harmonics enabled. Also, the phasor powermeter module 220 may be configured to provide for the polarity of eachinput, i.e. an identification of whether an input should be added orsubtracted when computing a sum.

[0233] Like the program objects that perform the functions of the phasormodules 200, the program object that performs the functions of thephasor power meter module 220 is not necessarily restricted to aspecific physical location. For example, the phasor power meter module220 may reside on a phasor transducer, such as the phasor transducer 51,or alternatively, the phasor power meter module 220 may reside on aphasor array processor, for example the phasor array processor 130. Ifthe program object that performs the functions of the phasor power metermodule is not physically located in the component that also includes thephasor modules, then the outputs of the modules 200 may be transmittedover the network 60 to another microprocessor where the appropriatephasor power meter module is located.

[0234] (3). Phasor Integration Module

[0235] Some of the values in the phasor power meter module outputregisters 226 are used as inputs by a phasor integration module 230.Like the phasor power meter module 220, the phasor integration module230 is preferably implemented as a program object. Specifically, thephasor integration module 230 uses as inputs the phasor array valuesfrom the phasor power meter output register 226. The phasor integrationmodule 230 also receives inputs that include (1) an “enable” input toenable operation of the phasor integration module 230, (2) a setupparameter that selects the harmonics that are enabled by the phasorintegration module, and (3) an input to reset the phasor integratormodule to zero.

[0236] The phasor integration module 230 performs a time integration ofselected input power phasor arrays to compute energy phasor arrays foreach enabled harmonic. The phasor integration module 230 providesoutputs in the form of a integration output register 236 and an eventregister 237. The integration output register 236 is composed of outputvalues that include a phasor array result that represents the timeintegration of the input phasor array. When the input to the phasorintegration module 230 is a power phasor array, the output array in theintegration output register 236 will be an energy phasor array whichrepresents the real and reactive energy for each harmonic which isenabled.

[0237] The phasor integration module 230 may be configured for selectionof a value for a divisor by which an integrand is divided before it isadded to the result. The phasor integration module 230 may also beconfigured for selection of an integration mode to specify the type ofintegration to be performed.

[0238] Like the program objects that perform the functions of the phasorpower meter module 220, the program object that performs the functionsof the phasor integration module 230 is not necessarily restricted to aspecific physical location and may reside on the phasor transducer 51,or on a phasor array processor. If the program object that performs thefunctions of the phasor integration module is not physically located inthe component that also includes the phasor power meter module 220, thenthe outputs of the phasor power meter module 220 may be transmitted overthe network 60 to another microprocessor where the phasor integrationmodule 230 is located.

[0239] (4). Inverse Time, Pulser, and Digital Output Modules

[0240] The phasor values in the current phasor array output registers206D-206G are provided as inputs to an inverse time module 240. Like thephasor modules 200, the phasor power module 220, and the integrationmodule 230, the inverse time module 240 is preferably implemented as aprogram object. The inverse time module 240 provides an overcurrentprotection function. (The inverse time module 240 may also be regardedas an inverse current module or an I2T module). The inverse time module240 receives the digital data from the phasor modules 200 and processesthe data to determine if there is a fault condition in the circuit 15.The inverse time module 240 also includes an “enable” input 241 thatenables the operation of the inverse time module 240.

[0241] The inverse time module 240 provide an output in the form ofinverse time output registers 246. The inverse time output registers 246include the following registers: (1) a state register 246A, (2) an I2Tvalue register 246B, and (3) an event register 246C. The inverse timemodule 240 may be configurable.

[0242] The state output register 246A of the inverse time module 240 isused as an input by a pulser module 250. The pulser module 250 may belocated on the phasor transducer 51. The pulser module 250 in turn hasan output register 256 that is used as an input by a digital outputmodule 260. The digital output module 260 is preferably located on thelocal processor of the protection device 185. Accordingly, in order forthe digital output module 260 to receive the data from the outputregister 256 of the pulser module 250, the data in the register 256 aretransmitted over the network 60 from the phasor transducer 51 to theprotection device 185. The digital output module 260 provides a tripoutput 266 that is coupled to the circuit breaker 45 (also shown inFIG. 1) associated with the circuit 15 the phasor values of which arebeing measured and computed by the phasor transducer 51.

[0243] The program objects that perform the functions of the inversetime module 240 and the pulser module 250 may reside on a phasortransducer, such as phasor transducer 51, or alternatively, thesemodules may reside on a phasor array processor, for example, the phasorarray processor 130. The digital output module 260 is preferably locatedon a local processor associated with the protection device 185associated with the circuit breaker 45. The digital output module 260receives its input from the pulser module 250 over the network 60.

[0244] (5). Communications Module

[0245] In a preferred embodiment, each phasor transducer also includes acommunications module 270. The communications module 270 is used to makethe data in the output registers of the modules 200, 220, 230, 240, 250,and 260 accessible to remote modules on other nodes on the network 60,such as the phasor array processor 130 and the protection device 185. Ina preferred embodiment, the communications module 270 allows externaldevices and/or modules to link to or communicate with any of the modulesor registers on the phasor transducer 51. The communications module 270preferably uses data communications techniques described in thecopending application Ser. No. 08/369,849, now U.S. Pat. No. 5,650,936.

[0246] If the modules 200, 220, 230, 240, and 250, are all locatedlocated on a single component, such as on the phasor transducer 51, theycan communicate with each other internally. However, if any of thesemodules are located on a remote microprocessor, such as a microprocessoron a phasor array processor or on a protection device, then thecommunications module 270 is used to enable the necessary data for theremote module to be accessible over the network 60.

[0247] (6). Other Modules on the Phasor Transducer

[0248] Other program modules may be located on a phasor transducerincluding a symmetrical component module, a recorder module, a setpointmodule, and arithmetic modules. The structure, function and operation ofthese modules are disclosed in the aforementioned copending applicationSer. No. 08/369,849, now U.S. Pat. No. 5,650,936. For example, asymmetrical component module may provide in its output registers valuesfor the positive, negative, and zero sequence current and voltagearrays.

[0249] (7). Phasor Summation Module

[0250]FIG. 4 is a functional diagram showing additional program objects.In a preferred embodiment, the program objects in FIG. 4 are located onthe phasor array processor 130. Some of the modules in FIG. 4 utilize astheir input the data in the output registers 206 of the modules 200 onthe plurality of the phasor transducers, such as the phasor transducers50, 51, 52, 53, and 54. Thus, the phasor array processor 130 is able toprocess phasor data from a plurality of circuits, such as the circuits14, 15, 16, 17, and 18. The program objects in FIG. 4 receive data fromthe phasor array transducers, 50, 51, 52, 53, and 54, over the network60. Alternatively, since the phasor transducers can communicate witheach other over the network 60, it is also possible to use a phasortransducer local microprocessor in one of the phasor transducers to runthe program objects in FIG. 4.

[0251] A phasor summation module 300 uses as its inputs the data in thevoltage and current output registers from the plurality of phasor powermodules located on the plurality of remote phasor transducers. Forexample, the phasor summation module 300 uses the data in the outputregisters 206 of the phasor modules 200 in the phasor transducer 51, aswell as corresponding data from the output registers 206 of the phasormodules in other phasor transducers, such as phasor transducers 50, 52,53, and 54. The summation module 300 receives these inputs over thenetwork 60 and may utilize a communication module for this purpose asdescribed below. The phasor summation module 300 also includes an enableinput 301 that enables operation of the module.

[0252] The phasor summation module 300 computes the vector sum of theinput phasor arrays from the plurality of phasor transducers.Specifically, the phasor summation module 300 computes the phasor sum ofall the current phasor array inputs and generates a current phasor arrayresult for each phase. The phasor summation module 300 also computes thepower phasor arrays for each voltage-current input pair, and sums themboth on a per-phase basis and on an all-phases basis. The resultingoutput is a net power phasor for each phase plus the net power phasorarrays for all phases.

[0253] The summation module 300 has the ability to buffer and time alignthe phasor array data from all the inputs so that the summationcalculation uses data which is representative of the same instant intime. In addition, the summation module 300 has the ability to assign apolarity to each input phasor array register. This allows the summationmodule 300 to compute net values that represent either total ordifferential current and power. Total values for current and power areadvantageous when it is desired to measure the total power delivered toa plurality of circuits. Differential values for current, power, andenergy are advantageous when it is desired to measure faults, powerlosses, or power delivered to a circuit which is not equipped with aphasor transducer device. Alternatively, instead of using voltage andcurrent phasor arrays, the summation module 300 may use power phasorarrays as input to achieve a similar functionality and result. (Notethat although the phasor summation module 300 may be used forcomputation of differential phasor values for current, power, andenergy, these functions may also be performed by a separate module, suchas the current differential module 340 described below. The computationof these differential values in the current differential module may beas a substitution for, or in addition to, the computation of thesevalues in the phasor summation module.)

[0254] The phasor summation module 300 provides its output in the formof summation output registers 306. The summation output registers 306include the following registers: (1) registers 306A, 306B, and 306Cwhich include a register for a net current phasor array for each phase,plus net RMS current parameter for each phase, (2) registers 306D, 306E,and 306F which include a register for a net power phasor array for eachphase, representing the total real and reactive power for each phase,(3) a register 306G including the net three phase power array,representing the total real and reactive power for all phases combined,(4) registers 306H, 306I, and 306J which include a register for the netpositive, negative, and zero sequence current, and (6) and an eventregister 306K.

[0255] The summation module 300 is configurable. The summation module300 may provide for configuration of type of phasor notation, e.g.polar, rectangular, complex, or exponential. The summation module 300may also be configured to select a desired scaling, e.g. per unit,percent, or Engineering. The summation module 300 may also be configuredto identify the voltage references, such as which voltage phasor arrayto associate with each current phasor array. In addition, the summationmodule 300 may be configured to provide for the selection of polarityfor each input in order to identify whether an input should be added orsubtracted when computing a sum.

[0256] (8). Current Differential Module

[0257] A current differential module 340 may also be included on thephasor array processor 130. Like the phasor summation module 300, thecurrent differential module 340 utilizes as its input the data from theoutput registers of a plurality of modules from a plurality of phasortransducers, such as the phasor transducers 50, 51, 52, 53, and 54,which represents phasor data from a plurality of circuits, such as thecircuits 14, 15, 16, 17, and 18. The current differential module 340receives these inputs over the network 60. The current differentialmodule 340 also includes an enable input 341 that enables operation ofthe module.

[0258] The current differential module 340 time aligns the phasorarrays, computes the phasor sum of the current phasor inputs, andgenerates a phasor result for each enabled harmonic. The result is thetotal current into the circuits, minus the total current out of thecircuits. In an ideal network of circuits, which is functioningcorrectly, this result will be zero. In a network of circuits with afault, or internal losses, the result will be a non-zero value. Thedifferential module also computes the sum of all the power phasors forall of the voltage and current phasor input pairs for each enabledharmonic. The result is the differential power phasor which provides thereal and reactive power losses in the circuits for each harmonic.

[0259] The current differential module 340 provides its output in theform of differential output registers 346. The differential outputregisters 346 include the following: (1) a register including thedifferential current for each harmonic 346A, (2) a register includingthe differential real power for each harmonic 346B, (3) a registerincluding the differential reactive power for each harmonic 346C, and(4) an event register 346D.

[0260] The current differential module 340 may be configurable forselection of type of phasor notation (e.g. polar, rectangular, complex,or exponential), scaling (e.g. per unit, percent, or Engineering),harmonic bands enabled, and voltage references (e.g. which voltagephasor to be associated with each current phasor).

[0261] As mentioned above, the functions of the current differentialmodule 340 may be performed by the phasor summation module 300.

[0262] (9). Summation Inverse Time Modules and Phasor Integration Moduleon the Phasor Array Processor

[0263] The present embodiment may also include phasor summation inversetime modules, such as a current phasor summation inverse time module 310and a power phasor summation inverse time module 320. Like the othermodules, these may be located on the phasor array processor 130 or maybe located elsewhere. These inverse time modules perform a similarfunction as the inverse time module 240, except that the inverse timemodules 310 and 320 use as their inputs the data in the phasor summationdata output registers 306 of the phasor summation module 300.Specifically, the current phasor inverse time module 310 uses the datafrom the current phasor summation registers 306A, 306B, and 306C and thepower phasor inverse time module 320 uses as its inputs the data fromthe power phasor summation registers 306D, 306E, and 306F. With regardto the current phasor summation inverse time module 310, this moduleperforms an overcurrent protection function based upon the summationcurrent phasor values. Since the summation phasor values are derived theseveral circuits, this module has the ability to perform its overcurrentprotection function based on the several circuits that are used to formthe summation net current phasor array for each phase. Similarly, withregard to the power phasor summation inverse time module 320, thismodule performs an overpower protection function based upon thesummation power phasor values derived the several circuits that are usedto form the summation power phasor array for each phase, representingthe total real and reactive power for each phase. Since the summationphasor values are derived the several circuits, this module has theability to perform its overpower protection function based on theseveral circuits that are used to form the summation net current phasorarray for each phase. These module permit sophisticated and highimpedance fault protection schemes to be implemented.

[0264] The current phasor summation inverse time module 310 provides anoutput in the form of current phasor inverse time output registers 316.The current phasor inverse time output registers 316 include thefollowing registers: (1) a state register 316A, (2) and (3) an eventregister 316B. The current phasor inverse time module 316 may beconfigurable.

[0265] Similarly, the power phasor summation inverse time module 320provides an output in the form of power phasor inverse time outputregisters 326. The power phasor inverse time output registers 326include the following registers: (1) a state register 326A, (2) and (3)an event register 326B. The power phasor inverse time module 32 may beconfigurable.

[0266] The state output register 316A of the current phasor inverse timemodule 310 and the state output register 326A of the power phasorinverse time module 320 are used as inputs by one or more pulser modules350. The pulser module 350 may be similar to the pulser module 250. Likethe pulser module 250, the pulser module 350 has an output register 356that is used as an input by a digital output module. The output register356 of the pulser module 350 may be used by more than one digital outputmodule associated with more than one circuit. Since the summationcurrent inverse time module 310 and the summation power inverse timemodule 320 represent values derived from several circuits, when anovercurrent or an overpower condition is detected based on the summationvalues, it may be desired to open more than one circuit. Accordingly,the output register 356 of the pulser module 350 may be sent to and usedby digital output modules (such as the digital output module 260)located on several respective protections devices associated withseparate circuits. Like the output 256 of the pulser module 250, theoutput 356 of the pulser module 350 may be transmitted over the datanetwork 60. Accordingly for this purpose, a communications module 280may be used, as described below.

[0267] (In an alternative embodiment, the pulser module 250 may be usedto receive the data from the output registers 316A and 326A of thesummation inverse time modules 310 and 320, respectively, and performthe functions of the pulser module 350.)

[0268] (10). Summation Phasor Integration Module on the Phasor ArrayProcessor

[0269] The present embodiment may also include a phasor summationintegration module 330. Like the other modules, this module may belocated on the phasor array processor 130 or may be located elsewhere.The phasor summation integration module 330 performs a similar functionas the phasor integration module 230, except that the phasor summationintegration module 330 uses as for its inputs the data in the phasorsummation data output register 306G of the phasor summation module 300.As mentioned above, the data from in phasor summation register 306Gincludes the net three phase power array, representing the total realand reactive power for all phases combined Since the summation phasorvalues are derived the several circuits, this module has the ability toprovide a time integration of phasor values, such as kilowatt-hours,except in the phasor domain. The phasor integration module 330 providesan output in the form of a phasor summation integration output register336A and an event register 336B.

[0270] The integration module 330 may be configured in a manner similarto the integration module 230.

[0271] (11). Communications Module on the Phasor Array Processor

[0272] In the embodiment in FIG. 4, the phasor array processor 130 alsoincludes a communications module 280. The communications module 280 isused to make the data in the output registers 306, 316,326, 336, and soon, of the phasor array processor 130 accessible to remote modules orother nodes on the network 60. The communications module 280 may besimilar or identical to the communications module 270 that runs on thelocal processor 100 of the node processor 51. (In general, acommunications module, such as 270 or 280, is associated with eachseparate device that has its own CPU and communications port andprovides for communications between the objects running on its CPU andobjects on other devices via its communications port.) Like thecommunications module 270, the communications module 280 allows externaldevices and/or modules to link to or communicate with any of the modulesor registers on the phasor array processor 130. The communicationsmodule 280 preferably uses data communications techniques described inthe aforementioned copending application Ser. No. 08/369,849, now U.S.Pat. No. 5,650,936.

[0273] The communications module 280 has a communications outputregister 286. The data in the communications output register 286 istransmitted via appropriate hardware such as a communications port ofthe phasor array processor 130 onto the data network 60.

[0274] (12). Other Modules on the Phasor Array Processor

[0275] A phasor power meter module, similar to the phasor power metermodule 220 described above, may be located on the phasor array processor130. A phasor power meter module located on the phasor array processor130 can be linked to phasor modules in remote phasor transducer devices.For example, if some phasor transducers do not have their own phasorpower meter modules, a phasor power meter module located on a phasorarray processor can be used to provide the power meter module functions.Similarly, if some voltage and current sensors are not connected to aphasor transducer, the outputs of the sensors can be digitized, put onthe network, provided to a phasor power meter module located on a phasorarray processor, and used to provide the power meter module functions.

[0276] (13). Other Modules on Other Processors

[0277] The system disclosed provides for protection, control, energymanagement, and systems diagnostics. The protection devices 184, 185,and so on operate to open circuits to provide protection based on thenot just the current or power conditions in a single circuit, but inmultiple circuits taking into account the inverse time module outputresults derived therefrom. The control and energy management functionsmay be provided by the power meter modules, summation modules, andintegration modules. The diagnostics function may be provided by all ofthese modules. In order to enable an operator to access the control,energy management, and systems diagnostics functions, a node on thenetwork may be provided with an appropriate module START HERE.

[0278] 7. System Synchronization

[0279] Referring to the synchronization circuit 120 in FIG. 2, it isnoted that by using a GPS-type signal, all the phasor transducers in thesystem, such as the phasor transducers 50, 51, 52, 53, and 54, can besynchronized to the same time reference. An advantage of such anarrangement is that all the phasor transducers can be configured tosample at the same time. However, such sampling may not necessarily besynchronous to the fundamental frequency of the electric power signal,thereby potentially introducing errors when the phasors are computedusing fast fourier transform techniques. This is true especially for theharmonic phasors. Moreover, the phasors will rotate if the sampling isnot done exactly synchronous to the fundamental frequency of theelectric power signal.

[0280] One alternative is to sample at a frequency which is an exactmultiple of the fundamental line frequency. This will provide foraccuracy when using fast fourier transform techniques to computephasors. However, this technique will not necessarily synchronize thesampling among the phasor transducers since the sample frequency may bedifferent at different phasor transducers. Further, when the phasor datais sent from the phasor transducers to the phasor array processors,computation becomes complicated because the different phasormeasurements need to be time aligned.

[0281] In a preferred embodiment, all the phasor transducers areconfigured to sample synchronously to the fundamental frequency at onepoint in the electricity distribution system signal. According to thepreferred embodiment, one of the phasor transducers is selected to actas a reference device for the entire system. The phasor for one of theinputs of this phasor transducer device becomes the reference phasor.The reference phasor transducer device computes the precise systemfrequency and the system “zero time reference” relative to the GPS-timeclock. These values are transmitted to each other phasor transducer inthe system which in turn sets its sampling to be simultaneous andsynchronous to the system reference frequency.

[0282] This arrangement has several advantages. All sampling is normallysynchronous (except when the system dynamics change) so that the fastfourier transform results and the phasors for the harmonics areaccurate. The phasors do not rotate except when the system dynamicschange so data transmission and storage requirements can be drasticallyreduced.

[0283] 8. Example

[0284] Referring to FIG. 5, an exemplary method of according to anembodiment will now be described.

[0285] One of the advantages of the disclosed system is its inherentability to provide sufficient information to properly handle electricprotection, control and metering functions at a network level ratherthan a circuit level. This advantage becomes apparent with regard tobreaker coordination. Conventional products generally perform at acircuit level.

[0286]FIG. 5 shows a typical three phase electricity distributionnetwork 400. The system 400 consists of two coupled substations, 402 and404, each with an incoming main, 402 a and 402 e, and a number of feedercircuits 402 b, 402 c, 402 d, 404 h, 404 i, 404 j, and 404 k. A seriousdesign problem in this type of network is breaker coordination. If afault occurs on the circuit 404 h, it may also be seen by the circuits402 a, 402 e, and 404 f. The problem is how to determine which circuitsto trip in addition to the circuit 404 h. According to prior systems,this is typically handled using either breaker coordination, zoneprotection, or trip blocking schemes. All of these methods are inexactand have functional limitations.

[0287] The phasor array processing capability as disclosed hereinprovides a superior solution to this problem. The phasor array processorcan sum the current phasor arrays for the circuits 402 a, 402 b, 402 c,402 d, and 402 e. If they add to zero, the circuit 402 a does not needto be opened, but if they add to a significant non zero value, thecircuit 402 a should be opened. Similarly the phasor array processor cansum the current phasor arrays for the circuits 404 f, 404 h, 404 i, 404j, and 404 k to determine if the circuit 404 f should be opened. Thephasor array processor can sum the current phasor arrays for thecircuits 402 e and 404 f to determine if there is a fault in the circuitbetween the circuits 402 e and 404 f.

[0288] An even more difficult situation for conventional devices isdetection and isolation of high impedance faults. If a high impedancefault occurs on the circuit 402 e, it is very difficult to detect andeven more difficult to isolate using conventional devices. The systemdisclosed above, including the phasor transducers and phasor arrayprocessor, can be used for high impedance detection and isolation. Thesystem can accomplish this by summing the current phasor arrays for thecircuits 402 e and 404 f. If they do not add to zero, it is assumed thatthere is a fault somewhere on the circuit 402 e. High impedance faultscan be detected and isolated to any segment of the circuit network whichis bounded by phasor transducer devices. This approach will work forboth low and high impedance faults.

[0289] Another problem solved by the above-disclosed system is networkloss monitoring. The losses in the substation 402 are equal to the sumof the power phasor arrays for the circuits 402 a, 402 b, 402 c, 402 d,and 402 e. The losses in the circuit between circuits 402 e and circuits404 f are equal to the sum of the power phasor arrays for the circuits402 e and 404 f. The losses in substation 404 are equal to the sum ofthe power phasor arrays for the circuits 404 f, 404 h, 404 i, 404 j, and404 k. This system allows power losses caused by loose connections, worncontactors, worn circuit breakers, or even power theft to be detectedand isolated. It is important to note that this system works even whenthere is a transformer in the circuit. Another feature of this approachis that it can be an effective way to verify the accuracy andperformance of each of the phasor transducer devices.

[0290] The disclosed system also provides effective protection andmetering redundancy, so functionality can be maintained even if anysingle device fails. For example, in FIG. 5, if the phasor transducerdevice in circuit 402 d fails, the power, current, and energy throughcircuit 402 d can still be derived by the phasor array processor usingthe formula phasor array (−402 d=phasor arrays 402 a+402 b+402 c+402 e).The phasor array processor can be configured so that it can trip thecircuit 402 d in the event of an over current situation through thatcircuit. Conventional devices are not capable of providing suchredundancy.

[0291] Those skilled in the art will recognize that similar results canbe achieved by using symmetrical component arrays instead of per phasephasor arrays.

[0292] Those skilled in the art will also appreciate that the phasortransducer embodiments could output data in different formats, such as awavelet format.

[0293] It is intended that the foregoing detailed description beregarded as illustrative rather than limiting and that it is understoodthat the following claims including all equivalents are intended todefine the scope of the embodiments.

We claim:
 1. A device for monitoring and reporting at least oneparameter of an electric circuit, said device comprising: at least onesensor coupled with said electric circuit and operative to sense atleast one electrical parameter in said electric circuit and generate atleast one analog signal indicative thereof; an analog to digitalconverter coupled with said at least one sensor and operative to convertsaid at least one analog signal to at least one digital signalrepresentative of said at least one analog signal; a processor coupledwith said analog to digital converter and operative to generate at leastone computed value from said at least one digital signal; a localdisplay coupled with said processor and operative to report saidcomputed value; a communications port coupled with said processor and adigital network and operative to facilitate reporting of said computedvalue onto said digital network; and a summing module coupled with saiddigital network, said summing module operative to receive said computedvalue and further sum said computed value to a second value.
 2. Thedevice of claim 1 further comprising a multiplexer coupled between saidat least one sensor and said analog to digital converter.
 3. The deviceof claim 1, wherein said analog to digital converter comprises first andsecond analog to digital converters, said first analog to digitalconverter being operative to convert a voltage analog signal to at leastone digital sample and said second analog to digital converter beingoperative to convert a current analog signal to at least one digitalsample.
 4. The device of claim 1, wherein said local display isoperative to display said at least one electrical parameter.
 5. Thedevice of claim 1, further comprising a time synchronization receiver,said processor operative to receive a first time synchronization signalfrom said time synchronization receiver whereby said processor isfurther operative to alter a timing clock signal based on said firsttime synchronization signal.
 6. The device of claim 5 further comprisinga local synchronization circuit, said local synchronization circuitoperative to output said timing clock signal to said processor.
 7. Thedevice of claim 5, wherein said first time synchronization signalcomprises a network time signal.
 8. The device of claim 5, wherein saidfirst time synchronization signal comprises a second timesynchronization signal from a second device coupled with said digitalnetwork.
 9. The device of claim 8, wherein said second timesynchronization signal from said second device is transmitted to aplurality of devices coupled with said digital network.
 10. The deviceof claim 5, wherein said time synchronization receiver comprises a GPSreceiver wherein said GPS receiver is operative to receive a GPS signal.11. The device of claim 10, wherein said GPS receiver wirelesslyreceives said GPS signal.
 12. The device of claim 5, wherein said firsttime synchronization signal is computed from a fundamental linefrequency computation of said electric circuit.
 13. The device of claim1 further comprising a remote module, said remote module operative toallow a second device to remotely connect to said device over saiddigital network.
 14. The device of claim 13, wherein said second devicecomprises at least one computer.
 15. The device of claim 13, whereinsaid second device comprises a meter.
 16. The device of claim 13,wherein said second device comprises a protection device.
 17. The deviceof claim 13, wherein said second device further comprises a secondremote module, said second remote module operative to allow said deviceto remotely connect to a third device over the digital network.
 18. Thedevice of claim 13, wherein said second device comprises a circuitbreaker, said circuit breaker comprising a second communications portcoupled with said digital network.
 19. The device of claim 1, whereinsaid digital network comprises an Ethernet network, said communicationsport comprising an Ethernet port.
 20. The device of claim 1, whereinsaid digital network comprises a digital data transmission network. 21.The device of claim 1, wherein said digital network comprises a TCP/IPcommunications network.
 22. The device of claim 1, wherein said digitalnetwork comprises a fiber optic data communications network.
 23. Thedevice of claim 1 further wherein said processor is operative to receivesaid one or more digital samples and provide digital data representativeof said electrical parameters.
 24. The device of claim 23 furtherwherein said device is operative to transmit said digital data onto saiddigital network.
 25. The device of claim 23, wherein said digital datais transmitted in substantially real time.
 26. The device of claim 1,said processor further comprising an inverse current module, saidinverse current module operative to determine a fault condition on saidelectric circuit.
 27. The device of claim 26, wherein said faultcondition is determined by calculating I²T.
 28. The device of claim 1,wherein said device is further coupled with at least a second electriccircuit, said device operative to perform an overcurrent protectionfunction.
 29. The device of claim 1 further comprising at least a secondcommunication port.
 30. The device of claim 29, wherein said at least asecond communication port comprises an Ethernet port.
 31. The device ofclaim 29, wherein said at least second communication port is coupledwith a second device.
 32. The device of claim 1 further comprising asecond communication port coupled with said digital network and a thirdcommunication port coupled with said digital network.
 33. The device ofclaim 32, wherein said second communication port and said thirdcommunication port each comprise at least one RS232 port.
 34. The deviceof claim 32, wherein said second communication port and said thirdcommunication port comprise at least one RS485 port.
 35. The device ofclaim 32, wherein said second communication port comprises an RS232 portand said third communication port comprises a RS485 port.
 36. The deviceof claim 1 wherein said communications port further is operative toscale said digital network for communications among additional of saidpower monitoring devices without substantially degrading real timecommunications among any at least two of said power monitoring devices.37. The device of claim 1, wherein said communications port enablescentralized simultaneous knowledge of a status of said plurality of saidpower monitoring devices.
 38. The device of claim 1, wherein saidcommunications port enables substantially simultaneous real timereporting of said computed value over said network from a plurality ofsaid devices without any one of said plurality of devices waiting foranother of said plurality of devices.
 39. The device of claim 1, whereinsaid digital network comprises a wireless network.
 40. The device ofclaim 1, wherein said communication port is further operative tocommunicate with substantially simultaneous connections with a pluralityof power monitoring devices over said digital network.
 41. The device ofclaim 1, wherein said summing module comprises a phasor summing module.42. The device of claim 1, wherein said summing module is coupled withsaid processor.
 43. A device for measuring electrical energy in anelectric circuit, said device comprising: at least one sensor coupledwith said electric circuit and operative to sense at least oneelectrical parameter in said electric circuit and generate at least oneanalog signal indicative thereof; at least one analog to digitalconverter coupled with said at least one sensor and operative to convertsaid at least one analog signal to at least one digital sample; a timesynchronization receiver operative to generate a time synchronizationsignal; and a processor coupled with said at least one analog to digitalconverter and said time synchronization receiver, said processoroperative to alter a timing clock signal based on said timesynchronization signal.
 44. The device of claim 43 further comprising alocal synchronization circuit coupled with said processor which outputssaid timing clock signal to said processor.
 45. The device of claim 43,wherein said time synchronization receiver is further coupled with acommunications network.
 46. The device of claim 45, wherein said timesynchronization receiver is operative to transmit said timesynchronization signal onto said communications network.
 47. The deviceof claim 43, wherein said time synchronization signal comprises anetwork time signal.
 48. The device of claim 43, wherein said timesynchronization signal comprises an external time synchronization signalgenerated externally to said device.
 49. The device of claim 43, whereinsaid time synchronization receiver comprises a GPS receiver operative toreceive a GPS signal.
 50. The device of claim 49, wherein said GPSreceiver is operative to wirelessly receive said GPS signal.
 51. Asystem for measuring the delivery of electrical energy from an energysupplier to a consumer through an electric circuit, said systemcomprising: a digital network; at least first and second devices coupledwith said digital network, said first and second devices eachcomprising: at least one sensor coupled with said electric circuit andoperative to sense at least one power parameter in said electric circuitand generate at least one analog signal indicative thereof; at least oneanalog to digital converter coupled with said at least one sensor andoperative to convert said at least one analog signal to at least onedigital signal representative thereof; a processor coupled with said atleast one analog to digital converter and operative to generate at leastone computed value from said at least one digital signal; and aplurality of communication ports, each of said communication portsoperative to receive input and transmit said input to said processor,said communication ports being coupled with said digital network,wherein said device is operative to engage in a plurality ofsubstantially simultaneous communications from said communication ports;whereby said first device communicates with at least said second deviceover said digital network.
 52. The system of claim 51, wherein at leastone of said first and second devices further comprises a localsynchronization circuit coupled with said processor which outputs atiming clock signal to said processor.
 53. The system of claim 51, saidfirst device further comprising a communications module, saidcommunications module operative to allow a device coupled to the digitalnetwork to communicate with said processor of said first device.
 54. Thesystem of claim 51, whereby said first device communicates with at leastsaid second device over said digital network substantially in real time.55. The system of claim 51, wherein said plurality of communicationports comprises at least one Ethernet port.
 56. The system of claim 51,wherein said plurality of communication ports comprises at least twoRS232 ports.
 57. The system of claim 51, wherein said plurality ofcommunication ports comprises at least two RS485 ports.
 58. The systemof claim 51, wherein said plurality of communication ports comprises atleast one Ethernet port and at least one of a RS232 port and a RS485port.
 59. A protection device for use with an electrical circuit, saidprotection device comprising: a communications port operative to couplesaid protection device with a data network; at least one output coupledwith said electric circuit and operative to control a flow of electricalpower through said electrical circuit; a processor coupled with saidcommunications port and said at least one output, said processorexecuting at least one programmable module, each of said at least oneprogrammable module operative to receive data from said communicationsport, process said data and generate a signal on said at least oneoutput to at least one of interrupt and restore said flow of electricalpower through said electrical circuit.
 60. The protection device ofclaim 59, wherein said data network comprises an Ethernet network. 61.The protection device of claim 59, wherein said electrical circuitcomprises at least one circuit breaker, said at least one output beingcoupled with said at least one circuit breaker to control operation ofsaid at least one circuit breaker.
 62. The protection device of claim61, wherein said at least one output is coupled with said at least onecircuit breaker via said digital network.
 63. The protection device ofclaim 59, wherein each of said at least one programmable modulecomprises at least one object oriented program module.
 64. Theprotection device of claim 59, wherein each of said at least oneprogrammable module comprises a plurality of programmable sub-modules,said plurality of programmable sub-modules capable of being linkedtogether to perform an arbitrary function.
 65. The protection device ofclaim 64, wherein said arbitrary function comprises a protectionfunction.
 66. The protection device of claim 64, wherein at least one ofsaid plurality of programmable sub-modules is operative to receive datafrom at least one other device coupled with said network.
 67. Theprotection device of claim 59, wherein said processor is furtheroperative to receive data from at least one other device coupled withsaid network.
 68. The protection device of claim 67, wherein said atleast one other device comprises at least one sensor coupled with saidelectric circuit and operative to sense at least one electricalparameter in said electric circuit, generate an analog signalrepresentative thereof, digitize said analog signal and transmit saiddigitized analog signal onto said digital network.
 69. The protectiondevice of claim 67, wherein said at least one other device comprises atleast one other protection device.
 70. The protection device of claim67, wherein said at least one programmable module comprises at least oneprogrammable sub-module coupled with said at least one other device toreceive said data.
 71. A protection device for use with an electricalcircuit, said protection device comprising: communications means forcoupling said protection device with a data network; output means forcoupling said protection device with said electric circuit to control aflow of electrical power through said electrical circuit; processormeans, coupled with said communications means and said output means,said processor means for executing at least one programmable modulemeans, each of said at least one programmable module means operative toreceive data from said communications means, process said data andgenerate a signal on said output means to at least one of interrupt andrestore said flow of electrical power through said electrical circuit.72. The protection device of claim 71, wherein said data networkcomprises an Ethernet network.
 73. The protection device of claim 71,wherein said electrical circuit comprises at least one circuit breaker,said output means being coupled with said at least one circuit breakerto control operation of said at least one circuit breaker.
 74. Theprotection device of claim 73, wherein said output means is coupled withsaid at least one circuit breaker via said digital network.
 75. Theprotection device of claim 71, wherein each of said at least oneprogrammable module means comprises at least one object oriented programmodule.
 76. The protection device of claim 71, wherein each of said atleast one programmable module means comprises a plurality ofprogrammable sub-module means, said plurality of programmable sub-modulemeans capable of being linked together to perform an arbitrary function.77. The protection device of claim 76, wherein said arbitrary functioncomprises a protection function.
 78. The protection device of claim 76,wherein at least one of said plurality of programmable sub-module meansis operative to receive data from at least one other device coupled withsaid network.
 79. The protection device of claim 71, wherein saidprocessor means is further operative to receive data from at least oneother device coupled with said network.
 80. The protection device ofclaim 79, wherein said at least one other device comprises at least onesensor means for sensing at least one electrical parameter in saidelectric circuit, generating an analog signal representative thereof,digitizing said analog signal and transmitting said digitized analogsignal onto said digital network.
 81. The protection device of claim 79,wherein said at least one other device comprises at least one otherprotection device.
 82. The protection device of claim 79, wherein saidat least one programmable module means comprises at least oneprogrammable sub-module means coupled with said at least one otherdevice to receive said data.
 83. A power control and monitoring system,comprising: an electrical power distribution network; a plurality ofprotection devices, each of said plurality of protection devices beingassociated with at least one portion of said electrical powerdistribution network and each of said plurality of protection devicesincluding a communications port for connection to a data network;wherein each of said plurality of protection devices includesuser-programmable logic, and wherein logic inputs and outputs arecommunicated between said plurality of protection devices over said datanetwork.